74LVT125; 74LVTH125
3.3 V quad buffer; 3-state
Rev. 8 — 18 August 2021
Product data sheet
1. General description
The 74LVT125; 74LVTH125 is a quad buffer/line driver with 3-state outputs controlled by the output
enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state.
Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs. This
device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables
the output, preventing the potentially damaging backflow current through the device when it is
powered down.
2. Features and benefits
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Quad bus interface
3-state buffers
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Wide supply voltage range from 2.7 to 3.6 V
BiCMOS high speed and output drive
Output capability: +64 mA and -32 mA
Direct interface with TTL levels
Overvoltage tolerant inputs to 5.5 V
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Power-up 3-state
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 500 mA per JESD 78 Class II Level B
Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)
ESD protection:
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HBM EIA/JESD22-A114-A exceeds 2000V
MM EIA/JESD22-A115-A exceeds 200V
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Specified from -40 °C to 85 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVT125D
-40 °C to +85 °C
-40 °C to +85 °C
-40 °C to +85 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LVTH125D
74LVT125PW
74LVTH125PW
74LVT125BQ
74LVTH125BQ
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
SOT762-1
DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm