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74LVT574BQ PDF预览

74LVT574BQ

更新时间: 2024-11-26 06:31:55
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
16页 109K
描述
3.3 V octal D-type flip-flop; 3-state

74LVT574BQ 数据手册

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74LVT574; 74LVTH574  
3.3 V octal D-type flip-flop; 3-state  
Rev. 04 — 11 September 2008  
Product data sheet  
1. General description  
The 74LVT574; 74LVTH574 is a high-performance product designed for VCC operation at  
3.3 V.  
This device is an 8-bit, edge triggered register coupled to eight 3-state output buffers. The  
two sections of the device are controlled independently by the clock (pin CP) and output  
enable (pin OE) control gates. The state of each D input (one setup time before the  
LOW-to-HIGH clock transition) is transferred to the corresponding flip-flops Q output.  
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS  
memories, or MOS microprocessors.  
The active LOW output enable (pin OE) controls all eight 3-state buffers independent of  
the clock operation.  
When pin OE is LOW, the stored data appears at the outputs. When pin OE is HIGH, the  
outputs are in the high-impedance OFF-state, which means they will neither drive nor load  
the bus.  
2. Features  
I Inputs and outputs arranged for easy interfacing to microprocessors  
I 3-state outputs for bus interfacing  
I Common output enable control  
I TTL input and output switching levels  
I Input and output interface capability to systems at 5 V supply  
I Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs  
I Live insertion and extraction permitted  
I No bus current loading when output is tied to 5 V bus  
I Power-up reset  
I Power-up 3-state  
I Latch-up protection  
N JESD78 class II exceeds 500mA  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I Specified from 40 °C to +85 °C  

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