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74LVT322373GX PDF预览

74LVT322373GX

更新时间: 2024-09-15 23:24:27
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路信息通信管理
页数 文件大小 规格书
6页 163K
描述
LATCH|QUAD|8-BIT|LVT/ALVT-BICMOS|BGA|96PIN|PLASTIC

74LVT322373GX 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:5.50 MM, PLASTIC, MO-205, FBGA-96针数:96
Reach Compliance Code:unknown风险等级:5.63
Is Samacsys:N系列:LVT
JESD-30 代码:R-PBGA-B96长度:13.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.012 A位数:8
功能数量:4端口数量:2
端子数量:96最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA96,6X16,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
包装方法:TAPE AND REEL电源:3.3 V
传播延迟(tpd):5.8 ns认证状态:Not Qualified
座面最大高度:1.4 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM宽度:5.5 mm
Base Number Matches:1

74LVT322373GX 数据手册

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May 2002  
Revised May 2002  
74LVT322373 74LVTH322373  
Low Voltage 32-Bit Transparent Latch  
with 3-STATE Outputs  
and 25Series Resistors in the Outputs  
General Description  
Features  
Input and output interface capability to systems at  
The LVT322373 and LVTH322373 contain thirty-two non-  
inverting latches with 3-STATE outputs and are intended  
for bus oriented applications. The device is byte controlled.  
The flip-flops appear transparent to the data when the  
Latch Enable (LE) is HIGH. When LE is LOW, the data that  
meets the setup time is latched. Data appears on the bus  
when the Output Enable (OE) is LOW. When OE is HIGH,  
the outputs are in a high impedance state.  
5V VCC  
Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH322373),  
also available without bushold feature (74LVT322373)  
Live insertion/extraction permitted  
Power Up/Down high impedance provides glitch-free  
bus loading  
The LVTH322373 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
Outputs include equivalent series resistance of 25to  
make external termination resistors unnecessary and  
reduce overshoot and undershoot  
These latches are designed for low voltage (3.3V) VCC  
applications, but with the capability to provide a TTL inter-  
ESD performance:  
Human-body model > 2000V  
face to  
a
5V environment. The LVT322373 and  
LVTH322373 are fabricated with an advanced BiCMOS  
technology to achieve high speed operation similar to 5V  
ABT while maintaining a low power dissipation.  
Machine model > 200V  
Charged-device model > 1000V  
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74LVT322373G  
(Note 1) (Note 2)  
BGA96A  
(Preliminary)  
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
74LVTH322373G  
(Note 1) (Note 2)  
BGA96A  
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
Note 1: Ordering Code “G” indicates Trays.  
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
© 2002 Fairchild Semiconductor Corporation  
DS500742  
www.fairchildsemi.com  

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