Datasheet > 74LVT16501A_06

74LVT16501A_06

更新时间： 2024-09-14 08:04:27

品牌	Logo	应用领域
恩智浦 - NXP		总线收发器
页数	文件大小	规格书
19页	107K
描述
3.3 V LVT 18-bit universal bus transceiver; 3-state

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74LVT16501A_06 数据手册

74LVT16501A

3.3 V LVT 18-bit universal bus transceiver; 3-state

Rev. 04 — 19 May 2006

Product data sheet

1. General description

The 74LVT16501A is a high-performance BiCMOS product designed for V_CCoperation at

3.3 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus

compatible outputs in both send and receive directions.

Data ﬂow in each direction is controlled by output enable (OEAB and OEBA), latch enable

(LEAB and LEBA), and clock (CPAB and CPBA) inputs.

For A-to-B data ﬂow, the device operates in the transparent mode when LEAB is HIGH.

When LEAB is LOW, the A-bus data is latched if CPAB is held at a HIGH or LOW level.

If LEAB is LOW, the A-bus data is stored in the latch/ﬂip-ﬂop on the LOW-to-HIGH

transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the

outputs are in the high-impedance state.

Data ﬂow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The

output enables are complimentary (OEAB is active HIGH and OEBA is active LOW).

Active bus hold circuitry is provided to hold unused or ﬂoating data inputs at a valid logic

level.

2. Features

I 18-bit bidirectional bus interface

I 3-state buffers

I Output capability: +64 mA to −32 mA

I TTL input and output switching levels

I Input and output interface capability to systems at 5 V supply

I Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs

I Live insertion and extraction permitted

I Power-up reset

I Power-up 3-state

I No bus current loading when output is tied to 5 V bus

I Positive-edge triggered clock inputs

I Latch-up protection:

N JESD78: exceeds 500 mA

I ESD protection:

N MIL STD 883, method 3015: exceeds 2000 V

N Machine model: exceeds 200 V

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