Datasheet > 74LVT16500ADL,118

74LVT16500ADL,118

更新时间： 2024-09-16 19:57:43

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
19页	98K
描述
74LVT16500A - 3.3 V 18-bit universal bus transceiver; 3-state SSOP 56-Pin

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74LVT16500ADL,118 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	生命周期：	Transferred
零件包装代码：	SSOP	包装说明：	7.50 MM, PLASTIC, MO-118, SOT-371-1, SSOP-56
针数：	56	Reach Compliance Code：	unknown
风险等级：	5.7	Base Number Matches：	1

74LVT16500ADL,118 数据手册

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74LVT16500A

3.3 V 18-bit universal bus transceiver; 3-state

Rev. 03 — 29 May 2006

Product data sheet

1. General description

The 74LVT16500A is a high-performance BiCMOS product designed for V_CCoperation at

3.3 V.

This device is an 18-bit universal transceiver featuring non-inverting 3-state bus

compatible outputs in both send and receive directions. Data ﬂow in each direction is

controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock

(CPAB and CPBA) inputs. For A-to-B data ﬂow, the device operates in the transparent

mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a

HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/ﬂip-ﬂop on

the HIGH-to-LOW transition of CPAB. When OEAB is HIGH, the outputs are active. When

OEAB is LOW, the outputs are in the high-impedance state.

Data ﬂow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The

output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW).

Active bus-hold circuitry is provided to hold unused or ﬂoating data inputs at a valid logic

level.

2. Features

I 18-bit bidirectional bus interface

I 3-state buffers

I Output capability: +64 mA and −32 mA

I TTL input and output switching levels

I Input and output interface capability to systems at 5 V supply

I Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused

inputs

I Live insertion/extraction permitted

I Power-up reset

I Power-up 3-state

I No bus current loading when output is tied to 5 V bus

I Negative edge-triggered clock inputs

I Latch-up protection:

N JESD78: exceeds 500 mA

I ESD protection:

N MIL STD 883 Method 3015: exceeds 2000 V

N CDM JESD22-C101-C exceeds 1000 V

12 3 4 5 6 7...19

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与74LVT16500ADL,118相关器件

型号	品牌	获取价格	描述	数据表
74LVT16500ADL,512	NXP	获取价格	74LVT16500A - 3.3 V 18-bit universal bus transceiver; 3-state SSOP 56-Pin
74LVT16500ADL,518	NXP	获取价格	74LVT16500A - 3.3 V 18-bit universal bus transceiver; 3-state SSOP 56-Pin
74LVT16500ADL-T	ETC	获取价格	18-Bit Bus Transceiver
74LVT16500DGGRE4	TI	获取价格	3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
74LVT16501A	NXP	获取价格	3.3V LVT 18-bit universal bus transceiver 3-State
74LVT16501A_06	NXP	获取价格	3.3 V LVT 18-bit universal bus transceiver; 3-state
74LVT16501ADGG	NXP	获取价格	3.3V LVT 18-bit universal bus transceiver 3-State
74LVT16501ADGG,112	NXP	获取价格	74LVT16501A - 3.3 V LVT 18-bit universal bus transceiver; 3-state TSSOP 56-Pin
74LVT16501ADGG-T	NXP	获取价格	IC LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.1 MM, PLASTIC, MO-153
74LVT16501ADGGY	NXP	获取价格	暂无描述

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