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74LVT16244MEA_NL PDF预览

74LVT16244MEA_NL

更新时间: 2024-10-26 13:04:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
7页 92K
描述
Bus Driver, LVT Series, 4-Func, 4-Bit, True Output, BICMOS, PDSO48, 0.300 INCH, LEAD FREE, MO-118, SSOP-48

74LVT16244MEA_NL 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:0.300 INCH, LEAD FREE, MO-118, SSOP-48针数:48
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.03Is Samacsys:N
系列:LVTJESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:15.875 mm
逻辑集成电路类型:BUS DRIVER位数:4
功能数量:4端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH传播延迟(tpd):3.9 ns
认证状态:Not Qualified座面最大高度:2.74 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
宽度:7.495 mmBase Number Matches:1

74LVT16244MEA_NL 数据手册

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March 1999  
Revised June 2005  
74LVT16244 74LVTH16244  
Low Voltage16-Bit Buffer/Line Driver  
with 3-STATE Outputs  
General Description  
Features  
Input and output interface capability to systems at  
The LVT16244 and LVTH16244 contain sixteen non-invert-  
ing buffers with 3-STATE outputs designed to be employed  
as a memory and address driver, clock driver, or bus ori-  
ented transmitter/receiver. The device is nibble controlled.  
Individual 3-STATE control inputs can be shorted together  
for 8-bit or 16-bit operation.  
5V VCC  
Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH16244),  
also available without bushold feature (74LVT16244).  
Live insertion/extraction permitted  
The LVTH16244 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
Power Up/Down high impedance provides glitch-free  
bus loading  
Outputs source/sink 32 mA/ 64 mA  
Functionally compatible with the 74 series 16244  
Latch-up performance exceeds 500 mA  
ESD performance:  
These buffers and line drivers are designed for low-voltage  
(3.3V) VCC applications, but with the capability to provide a  
TTL interface to a 5V environment. The LVT16244 and  
LVTH16244 are fabricated with an advanced BiCMOS  
technology to achieve high speed operation similar to 5V  
ABT while maintaining a low power dissipation  
Human-body model 2000V  
Machine model 200V  
Charged-drive model 1000V  
Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA)  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LVT16244G  
(Note 1)(Note 2)  
BGA54A  
(Preliminary)  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
74LVT16244MEA  
(Note 2)  
MS48A  
MTD48  
BGA54A  
MS48A  
MTD48  
74LVT16244MTD  
(Note 2)  
74LVTH16244G  
(Note 1)(Note 2)  
74LVTH16244MEA  
(Note 2)  
74LVTH16244MTD  
(Note 2)  
Note 1: Ordering code “G” indicates Trays.  
Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
© 2005 Fairchild Semiconductor Corporation  
DS500151  
www.fairchildsemi.com  

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