June 1999
Revised June 1999
74LVT162240 • 74LVTH162240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3-STATE Outputs and
25Ω Series Resistors in the Outputs
advanced BiCMOS technology to achieve high speed oper-
ation similar to 5V ABT while maintaining a low power dis-
sipation.
General Description
The LVT162240 and LVTH162240 contain sixteen inverting
buffers with 3-STATE outputs designed to be employed as
a memory and address driver, clock driver, or bus oriented
transmitter/receiver. The device is nibble controlled. Indi-
vidual 3-STATE control inputs can be shorted together for
8-bit or 16-bit operation.
Features
■ Input and output interface capability to systems at
5V VCC
The LVT162240 and LVTH162240 are designed with
equivalent 25Ω series resistance in both the HIGH and
LOW states of the output. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
■ Outputs include equivalent series resistance of 25Ω to
make external termination resistors unnecessary and
reduce overshoot and undershoot
■ Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH162240),
also available without bushold feature (74LVT162240).
The LVTH162240 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
These inverting buffers and line drivers are designed for
low-voltage (3.3V) VCC applications, but with the capability
■ Functionally compatible with the 74 series 162240
■ Latch-up performance exceeds 500 mA
to provide a TTL interface to a 5V environment. The
LVT162240 and LVTH162240 are fabricated with an
Ordering Code:
Order Number
74LVT162240MEA
74LVT162240MTD
74LVTH162240MEA
74LVTH162240MTD
Package Number
MS48A
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MTD48
MS48A
MTD48
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
Output Enable Inputs (Active LOW)
Inputs
I0–I15
O0–O15
3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation
DS012490
www.fairchildsemi.com