74LVQ245SJ

更新时间： 2024-11-18 04:47:51

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		总线驱动器总线收发器逻辑集成电路光电二极管
页数	文件大小	规格书
12页	282K
描述
Low Voltage Octal Bidirectional Transceiver

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数据手册

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74LVQ245SJ 数据手册

74LVQ245

LOW VOLTAGE CMOS OCTAL BUS

TRANSCEIVER WITH (3-STATE)

■

HIGH SPEED:

= 5.7 ns (TYP.) at V = 3.3 V

■

COMPATIBLE WITH TTL OUTPUTS

LOW POWER DISSIPATION:

= 5 µA (MAX.) at T =25°C

■

LOW NOISE:

= 0.5V (TYP.) at V = 3.3V

75Ω TRANSMISSION LINE DRIVING

CAPABILITY

SYMMETRICAL OUTPUT IMPEDANCE:

SOP

TSSOP

OLP

Table 1: Order Codes

PACKAGE

|I | = I = 12mA (MIN) at V = 3.0 V

T & R

■

PCI BUS LEVELS GUARANTEED AT 24 mA

BALANCED PROPAGATION DELAYS:

SOP

74LVQ245MTR

74LVQ245TTR

TSSOP

PHL

PLH

■

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 3.6V (1.2V Data Retention)

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 245

This IC is intended for two-way asynchronous

communication between data buses and the

direction of data transmission is determined by

DIR input. The enable input G can be used to

disable the device so that the buses are effectively

isolated.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74LVQ245 is a low voltage CMOS OCTAL

BUS TRANSCEIVER (3-STATE fabricated with

sub-micron silicon gate and double-layer metal

wiring C MOS technology. It is ideal for low power

and low noise 3.3V applications.

All floating bus terminals during High Impedance

State must be held HIGH or LOW.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 5

1/12

July 2004

12 3 4 5 6 7...12

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74LVQ245SJX	FAIRCHILD	获取价格	Bus Transceiver, LVQ Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, EIAJ TYPE2
74LVQ245T	STMICROELECTRONICS	获取价格	LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER 3-STATE
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74LVQ273_04	FAIRCHILD	获取价格	OCTAL D-TYPE FLIP FLOP WITH CLEAR
74LVQ273M	STMICROELECTRONICS	获取价格	OCTAL D-TYPE FLIP FLOP WITH CLEAR
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