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74LVQ245SC PDF预览

74LVQ245SC

更新时间: 2024-11-20 04:47:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 282K
描述
Low Voltage Octal Bidirectional Transceiver

74LVQ245SC 数据手册

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74LVQ245  
LOW VOLTAGE CMOS OCTAL BUS  
TRANSCEIVER WITH (3-STATE)  
HIGH SPEED:  
= 5.7 ns (TYP.) at V = 3.3 V  
t
PD  
CC  
COMPATIBLE WITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
I
= 5 µA (MAX.) at T =25°C  
CC  
A
LOW NOISE:  
= 0.5V (TYP.) at V = 3.3V  
75TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
V
SOP  
TSSOP  
OLP  
CC  
Table 1: Order Codes  
PACKAGE  
|I | = I = 12mA (MIN) at V = 3.0 V  
OH  
OL  
CC  
T & R  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
SOP  
74LVQ245MTR  
74LVQ245TTR  
TSSOP  
t
t
PHL  
PLH  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 245  
This IC is intended for two-way asynchronous  
communication between data buses and the  
direction of data transmission is determined by  
DIR input. The enable input G can be used to  
disable the device so that the buses are effectively  
isolated.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
V
CC  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The 74LVQ245 is a low voltage CMOS OCTAL  
BUS TRANSCEIVER (3-STATE fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C MOS technology. It is ideal for low power  
and low noise 3.3V applications.  
2
All floating bus terminals during High Impedance  
State must be held HIGH or LOW.  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 5  
1/12  
July 2004  

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