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74LVQ245MTR PDF预览

74LVQ245MTR

更新时间: 2024-11-17 04:47:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 282K
描述
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER WITH (3-STATE)

74LVQ245MTR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.21
Is Samacsys:N其他特性:WITH DIRECTION CONTROL
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:LVQJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.024 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:12 ns
传播延迟(tpd):15 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:7.5 mmBase Number Matches:1

74LVQ245MTR 数据手册

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74LVQ245  
LOW VOLTAGE CMOS OCTAL BUS  
TRANSCEIVER WITH (3-STATE)  
HIGH SPEED:  
= 5.7 ns (TYP.) at V = 3.3 V  
t
PD  
CC  
COMPATIBLE WITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
I
= 5 µA (MAX.) at T =25°C  
CC  
A
LOW NOISE:  
= 0.5V (TYP.) at V = 3.3V  
75TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
V
SOP  
TSSOP  
OLP  
CC  
Table 1: Order Codes  
PACKAGE  
|I | = I = 12mA (MIN) at V = 3.0 V  
OH  
OL  
CC  
T & R  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
SOP  
74LVQ245MTR  
74LVQ245TTR  
TSSOP  
t
t
PHL  
PLH  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 245  
This IC is intended for two-way asynchronous  
communication between data buses and the  
direction of data transmission is determined by  
DIR input. The enable input G can be used to  
disable the device so that the buses are effectively  
isolated.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
V
CC  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The 74LVQ245 is a low voltage CMOS OCTAL  
BUS TRANSCEIVER (3-STATE fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C MOS technology. It is ideal for low power  
and low noise 3.3V applications.  
2
All floating bus terminals during High Impedance  
State must be held HIGH or LOW.  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 5  
1/12  
July 2004  

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