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74LVQ245 PDF预览

74LVQ245

更新时间: 2024-11-29 22:53:19
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线收发器
页数 文件大小 规格书
8页 67K
描述
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER 3-STATE

74LVQ245 数据手册

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74LVQ245  
LOW VOLTAGE CMOS OCTAL BUS  
TRANSCEIVER (3-STATE)  
HIGH SPEED:tPD =6 ns (TYP.) atVCC =3.3V  
COMPATIBLEWITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
o
µ
I
CC =5 A (MAX.) at TA =25 C  
LOWNOISE:VOLP = 0.5V(TYP.) at VCC =3.3V  
75TRANSMISSIONLINEDRIVING  
CAPABILITY  
M
T
(Micro Package)  
(TSSOPPackage)  
ORDER CODES :  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 12 mA (MIN)  
74LVQ245M  
74LVQ245T  
PCI BUSLEVELSGUARANTEED AT 24mA  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
This IC is intended for two-way asynchronous  
communication between data buses; the direction  
of data trasmission is determined by DIR input.  
The enable input G can be used to disable the  
device so that the buses are effectively isolated.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 3.6V (1.2VData Retention)  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES245  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The LVQ245 is a low voltage CMOS OCTAL BUS  
TRANSCEIVER (3-STATE) fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology. It is ideal for low  
power and low noise 3.3V applications.  
It has better speed performance at 3.3V than 5V  
LSTTL family combined with the true CMOS low  
power consumption.  
IT IS PROHIBITED TO APPLY A SIGNAL TO A  
TERMINAL WHEN IT IS IN OUTPUT MODE  
AND WHEN A BUS TERMINAL IS FLOATING  
(HIGH IMPEDANCE STATE) IT IS REQUESTED  
TO FIX THE INPUT LEVEL BY MEANS OF  
EXTERNAL PULL DOWN OR PULL UP  
RESISTOR.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
March 1999  

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