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74LVQ240SC PDF预览

74LVQ240SC

更新时间: 2024-02-04 02:18:27
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
6页 92K
描述
Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

74LVQ240SC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.68
Is Samacsys:N控制类型:ENABLE LOW
系列:LVQJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:11 ns
传播延迟(tpd):14 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

74LVQ240SC 数据手册

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May 1998  
74LVQ240  
Low Voltage Octal Buffer/Line Driver with 3-STATE  
Outputs  
General Description  
Features  
n Ideal for low power/low noise 3.3V applications  
n Implements patented EMI reduction circuitry  
The LVQ240 is an inverting octal buffer and line driver de-  
signed to be employed as a memory address driver, clock  
driver and bus oriented transmitter or receiver which pro-  
vides improved PC board density.  
n Available in SOIC JEDEC, SOIC EIAJ, and QSOP  
packages  
n Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
n Improved latch-up immunity  
n Guaranteed incident wave switching into 75  
n 4 kV minimum ESD immunity  
Ordering Code:  
Order Number  
74LVQ240SC  
74LVQ240SJ  
Package Number  
M20B  
Package Description  
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC  
20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ  
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC  
M20D  
74LVQ240QSC  
MQA20  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Assignment,  
SOIC and QSOP  
DS011611-1  
Pin Descriptions  
Pin Names  
Description  
OE1, OE2  
I0–I7  
3-STATE Output Enable Inputs  
DS011611-2  
Inputs  
Truth Tables  
O0–O7  
Outputs  
Inputs  
Outputs  
(Pins 12, 14, 16, 18)  
OE1  
L
In  
L
H
X
H
L
L
H
Z
Inputs  
Outputs  
OE2  
L
In  
L
(Pins 3, 5, 7, 9)  
H
L
L
H
X
H
Z
=
=
=
=
H
X
HIGH Voltage Level  
Immaterial  
L
Z
LOW Voltage Level  
High Impedance  
© 1998 Fairchild Semiconductor Corporation  
DS011611  
www.fairchildsemi.com  

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