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74LVQ240QSC PDF预览

74LVQ240QSC

更新时间: 2024-11-16 22:53:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 92K
描述
Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

74LVQ240QSC 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SSOP包装说明:0.150 INCH, MO-137, QSOP-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.45
Is Samacsys:N控制类型:ENABLE LOW
系列:LVQJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.012 A湿度敏感等级:1
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:TUBE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:10.5 ns传播延迟(tpd):15 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9116 mmBase Number Matches:1

74LVQ240QSC 数据手册

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May 1998  
74LVQ240  
Low Voltage Octal Buffer/Line Driver with 3-STATE  
Outputs  
General Description  
Features  
n Ideal for low power/low noise 3.3V applications  
n Implements patented EMI reduction circuitry  
The LVQ240 is an inverting octal buffer and line driver de-  
signed to be employed as a memory address driver, clock  
driver and bus oriented transmitter or receiver which pro-  
vides improved PC board density.  
n Available in SOIC JEDEC, SOIC EIAJ, and QSOP  
packages  
n Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
n Improved latch-up immunity  
n Guaranteed incident wave switching into 75  
n 4 kV minimum ESD immunity  
Ordering Code:  
Order Number  
74LVQ240SC  
74LVQ240SJ  
Package Number  
M20B  
Package Description  
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC  
20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ  
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC  
M20D  
74LVQ240QSC  
MQA20  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Pin Assignment,  
SOIC and QSOP  
DS011611-1  
Pin Descriptions  
Pin Names  
Description  
OE1, OE2  
I0–I7  
3-STATE Output Enable Inputs  
DS011611-2  
Inputs  
Truth Tables  
O0–O7  
Outputs  
Inputs  
Outputs  
(Pins 12, 14, 16, 18)  
OE1  
L
In  
L
H
X
H
L
L
H
Z
Inputs  
Outputs  
OE2  
L
In  
L
(Pins 3, 5, 7, 9)  
H
L
L
H
X
H
Z
=
=
=
=
H
X
HIGH Voltage Level  
Immaterial  
L
Z
LOW Voltage Level  
High Impedance  
© 1998 Fairchild Semiconductor Corporation  
DS011611  
www.fairchildsemi.com  

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