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74LVQ174SJ PDF预览

74LVQ174SJ

更新时间: 2024-11-19 04:47:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
13页 302K
描述
Low Voltage Hex D-Type Flip-Flop with Master Reset

74LVQ174SJ 数据手册

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74LVQ174  
HEX D-TYPE FLIP FLOP WITH CLEAR  
HIGH SPEED:  
= 150 MHz (TYP.) at V = 3.3 V  
f
MAX  
CC  
COMPATIBLE WITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
I
= 4 µA (MAX.) at T =25°C  
CC  
A
LOW NOISE:  
= 0.3V (TYP.) at V = 3.3V  
75TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
SOP  
TSSOP  
V
OLP  
CC  
Table 1: Order Codes  
PACKAGE  
|I | = I = 12mA (MIN) at V = 3.0 V  
T & R  
OH  
OL  
CC  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
SOP  
74LVQ174MTR  
74LVQ174TTR  
TSSOP  
t
t
PHL  
PLH  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 174  
technology. It is ideal for low power and low noise  
3.3V applications.  
Information signals applied to D inputs are  
transferred to the Q outputs on the positive going  
edge of the CLK pulse.  
V
CC  
IMPROVED LATCH-UP IMMUNITY  
When the CLR input is held low, the Q outputs are  
held low independently of the other inputs.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74LVQ174 is a low voltage CMOS HEX  
D-TYPE FLIP FLOP WITH CLEAR NON  
INVERTING fabricated with sub-micron silicon  
2
gate and double-layer metal wiring C MOS  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 5  
1/13  
July 2004  

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