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74LVQ163_04 PDF预览

74LVQ163_04

更新时间: 2024-11-20 04:47:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器
页数 文件大小 规格书
14页 370K
描述
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

74LVQ163_04 数据手册

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74LVQ163  
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER  
HIGH SPEED:  
= 180 MHz (TYP.) at V = 3.3 V  
f
MAX  
CC  
COMPATIBLE WITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
I
= 4 µA (MAX.) at T =25°C  
A
CC  
LOW NOISE:  
= 0.3V (TYP.) at V = 3.3V  
75TRANSMISSION LINE DRIVING  
SOP  
TSSOP  
V
OLP  
CC  
CAPABILITY  
Table 1: Order Codes  
PACKAGE  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 12mA (MIN) at V = 3.0 V  
T & R  
OH  
OL  
CC  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
SOP  
74LVQ163MTR  
74LVQ163TTR  
TSSOP  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 163  
control inputs, Master Reset (CLEAR), Parallel  
Enable Input (LOAD), Count Enable Input (PE)  
and Count Enable Carry Input (TE), determine the  
mode of operation as shown in the Truth Table. A  
LOW signal on CLEAR overrides counting and  
parallel loading and allows all outputs to go LOW  
on the next rising edge of CLOCK. A LOW signal  
on LOAD overrides counting and allows  
information on Parallel Data Qn inputs to be  
loaded into the flip-flops on the next rising edge of  
CLOCK. With LOAD and CLEAR, PE and TE  
permit counting when both are high. Conversely, a  
LOW signal on either PE and TE inhibits counting.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
V
CC  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The 74LVQ163 is  
SYNCHRONOUS PRESETTABLE COUNTER  
fabricated with sub-micron silicon gate and  
double-layer metal wiring C MOS technology. It is  
ideal for low power and low noise 3.3V  
applications. It is a 4 bit binary counter with  
Synchronous Clear.  
The circuit have four fundamental modes of  
operation, in order of preference: synchronous  
reset, parallel load, count-up and hold. Four  
a
low voltage CMOS  
2
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 2  
1/14  
July 2004  

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