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74LVQ161M PDF预览

74LVQ161M

更新时间: 2024-11-19 23:24:27
品牌 Logo 应用领域
其他 - ETC 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
13页 107K
描述
COUNTER|UP|4-BIT BINARY|LVQ-CMOS|SOP|16PIN|PLASTIC

74LVQ161M 数据手册

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74LVQ161  
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER  
HIGH SPEED:  
= 180 MHz (TYP.) at V = 3.3 V  
f
MAX  
CC  
COMPATIBLE WITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
I
= 4 µA (MAX.) at T =25°C  
CC  
A
LOW NOISE:  
= 0.3V (TYP.) at V = 3.3V  
75TRANSMISSION LINE DRIVING  
SOP  
TSSOP  
V
OLP  
CC  
CAPABILITY  
ORDER CODES  
PACKAGE  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 12mA (MIN) at V = 3.0 V  
TUBE  
T & R  
OH  
OL  
CC  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
SOP  
74LVQ161M  
74LVQ161MTR  
74LVQ161TTR  
TSSOP  
t
t
PHL  
PLH  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 161  
reset, parallel load, count-up and hold. Four  
control inputs, Master Reset (CLEAR), Parallel  
Enable Input (PE) and Count Enable Carry Input  
(TE), determine the mode of operation as shown  
in the Truth Table. A LOW signal on CLEAR  
overrides counting and parallel loading and sets  
all outputs on LOW state. A LOW signal on LOAD  
overrides counting and allows information on  
Parallel Data Qn inputs to be loaded into the  
flip-flops on the next rising edge of CLOCK. With  
LOAD and CLEAR, PE and TE permit counting  
when both are high. Conversely, a LOW signal on  
either PE and TE inhibits counting. All inputs and  
outputs are equipped with protection circuits  
against static discharge, giving them 2KV ESD  
immunity and transient excess voltage.  
V
CC  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The 74LVQ161 is  
SYNCHRONOUS PRESETTABLE COUNTER  
fabricated with sub-micron silicon gate and  
double-layer metal wiring C MOS technology. It is  
ideal for low power and low noise 3.3V  
applications. It is a 4 bit binary counter with  
Asynchronous Clear.  
The circuit have four fundamental modes of  
operation, in order of preference: synchronous  
a
low voltage CMOS  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/13  

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