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74LVQ138_01 PDF预览

74LVQ138_01

更新时间: 2024-11-20 06:31:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 解码器解复用器
页数 文件大小 规格书
6页 71K
描述
Low Voltage 1-of-8 Decoder/Demultiplexer

74LVQ138_01 数据手册

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February 1992  
Revised June 2001  
74LVQ138  
Low Voltage 1-of-8 Decoder/Demultiplexer  
General Description  
Features  
Ideal for low power/low noise 3.3V applications  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
The LVQ138 is a high-speed 1-of-8 decoder/demultiplexer.  
This device is ideally suited for high-speed bipolar memory  
chip select address decoding. The multiple input enables  
allow parallel expansion to a 1-of-24 decoder using just  
three LVQ138 devices or a 1-of-32 decoder using four  
LVQ138 devices and one inverter.  
Improved latch-up immunity  
Guaranteed incident wave switching into 75  
4kV minimum ESD immunity  
Demultiplexing capability  
Multiple input enable for each expansion  
Active LOW mutually exclusive outputs  
Ordering Code:  
Order Number  
74LVQ138SC  
74LVQ138SJ  
Package Number  
M16A  
Package Description  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M16D  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
A0A2  
E1E2  
E3  
Description  
Address Inputs  
Enable Inputs  
Enable Input  
Outputs  
O0O7  
© 2001 Fairchild Semiconductor Corporation  
DS011350  
www.fairchildsemi.com  

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