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74LVQ138 PDF预览

74LVQ138

更新时间: 2024-11-19 22:53:19
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
9页 72K
描述
3 TO 8 LINE DECODER INVERTING

74LVQ138 数据手册

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74LVQ138  
3 TO 8 LINE DECODER (INVERTING)  
HIGH SPEED:tPD =5.5ns (TYP.) atVCC = 3.3V  
COMPATIBLEWITH TTL OUTPUT  
LOW POWER DISSIPATION:  
o
µ
I
CC =4 A (MAX.) at TA =25 C  
LOWNOISE:  
M1  
T
VOLP =0.2 V (TYP.)at VCC = 3.3V  
(Micro Package)  
(TSSOPPackage)  
75 TRANSMISSIONLINEDRIVING  
ORDER CODES :  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 12 mA (MIN)  
74LVQ138M  
74LVQ138T  
PCI BUSLEVELSGUARANTEED AT 24mA  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
If the device is enabled, 3 binary select inputs (A,  
B and C) determine which one of the outputs will  
go low. If enable input G1 is held low or either  
G2A or G2B is held high, the decoding function is  
inhibited and all the 8 outputsgo high.  
Three enable inputs are provided to ease  
cascade connection and application of address  
decodersfor memory systems.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 3.6V(1.2VDataRetention)  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES138  
IMPROVED LATCH-UP IMMUNITY  
It has better speed performance at 3.3V than 5V  
LSTTL family combinad with the true CMOS low  
power consumption.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The LVQ138 is a low voltage CMOS 3 TO 8 LINE  
DECODER  
(INVERTING)  
fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
It is ideal for low power and low noise 3.3V  
applications.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/9  
February 1999  

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