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74LVQ125 PDF预览

74LVQ125

更新时间: 2024-11-19 22:53:19
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
8页 64K
描述
QUAD BUS BUFFERS 3-STATE

74LVQ125 数据手册

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74LVQ125  
QUAD BUS BUFFERS (3-STATE)  
HIGH SPEED:tPD =5 ns (TYP.) atVCC =3.3V  
COMPATIBLEWITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
o
µ
ICC =4 A (MAX.) at TA =25 C  
M
T
LOWNOISE:  
(Micro Package)  
(TSSOPPackage)  
VOLP =0.3 V (TYP.)at VCC = 3.3V  
75 TRANSMISSIONLINEDRIVING  
ORDER CODES :  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 12 mA (MIN)  
PCI BUSLEVELSGUARANTEED AT 24mA  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
74LVQ125M  
74LVQ125T  
technology.It is ideal for low power and low noise  
3.3V applications.  
The device requires the same 3-STATE control  
input G to be set high to place the output in to the  
high impedance state.  
It has better speed performance at 3.3V than 5V  
LS-TTL family combined with the true CMOS low  
power consumption.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 3.6V(1.2VDataRetention)  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES125  
IMPROVED LATCH-UP IMMUNITY  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The LVQ125 is a low voltage CMOS QUAD BUS  
BUFFERS fabricated with sub-micron silicon gate  
and  
double-layer metal  
wiring  
C2MOS  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
February 1999  

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