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74LVQ11MTR PDF预览

74LVQ11MTR

更新时间: 2024-01-06 16:05:46
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
8页 160K
描述
TRIPLE 3-INPUT AND GATE

74LVQ11MTR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP14,.25
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.92
系列:LVQJESD-30 代码:R-PDSO-G14
JESD-609代码:e0长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:AND GATE
最大I(ol):0.024 A功能数量:3
输入次数:3端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:3.3 VProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):13 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.2 mm
子类别:Gates最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

74LVQ11MTR 数据手册

 浏览型号74LVQ11MTR的Datasheet PDF文件第2页浏览型号74LVQ11MTR的Datasheet PDF文件第3页浏览型号74LVQ11MTR的Datasheet PDF文件第4页浏览型号74LVQ11MTR的Datasheet PDF文件第5页浏览型号74LVQ11MTR的Datasheet PDF文件第6页浏览型号74LVQ11MTR的Datasheet PDF文件第7页 
74LVQ11  
TRIPLE 3-INPUT AND GATE  
HIGH SPEED:  
= 4.7ns (TYP.) at V = 3.3 V  
t
PD  
CC  
COMPATIBLE WITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
I
= 2µA (MAX.) at T =25°C  
A
CC  
LOW NOISE:  
= 0.3V (TYP.) at V = 3.3V  
75TRANSMISSION LINE DRIVING  
CAPABILITY  
SOP  
TSSOP  
V
OLP  
CC  
SYMMETRICAL OUTPUT IMPEDANCE:  
ORDER CODES  
PACKAGE  
|I | = I = 12mA (MIN) at V = 3.0 V  
OH  
OL  
CC  
TUBE  
T & R  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
SOP  
74LVQ11M  
74LVQ11MTR  
74LVQ11TTR  
TSSOP  
t
t
PHL  
PLH  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 11  
V
technology. It is ideal for low power and low noise  
3.3V applications.  
The internal circuit is composed of 3 stages  
including buffer output, which enables high noise  
immunity and stable output.  
CC  
IMPROVED LATCH-UP IMMUNITY  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74LVQ11 is a low voltage CMOS TRIPLE  
3-INPUT AND GATE fabricated with sub-micron  
2
silicon gate and double-layer metal wiring C MOS  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/8  

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