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74LVQ10M PDF预览

74LVQ10M

更新时间: 2024-11-19 23:24:27
品牌 Logo 应用领域
其他 - ETC 触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
8页 58K
描述
LOGIC GATE|3 3-INPUT NAND|LVQ-CMOS|SOP|14PIN|PLASTIC

74LVQ10M 数据手册

 浏览型号74LVQ10M的Datasheet PDF文件第2页浏览型号74LVQ10M的Datasheet PDF文件第3页浏览型号74LVQ10M的Datasheet PDF文件第4页浏览型号74LVQ10M的Datasheet PDF文件第5页浏览型号74LVQ10M的Datasheet PDF文件第6页浏览型号74LVQ10M的Datasheet PDF文件第7页 
74LVQ10  
TRIPLE 3-INPUT NAND GATE  
HIGH SPEED:  
= 5.3ns (TYP.) at V = 3.3 V  
t
PD  
CC  
COMPATIBLE WITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
I
= 2µA (MAX.) at T =25°C  
A
CC  
LOW NOISE:  
= 0.3V (TYP.) at V = 3.3V  
75TRANSMISSION LINE DRIVING  
CAPABILITY  
SOP  
TSSOP  
V
OLP  
CC  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 12mA (MIN) at V = 3.0 V  
ORDER CODES  
PACKAGE  
OH  
OL  
CC  
TUBE  
T & R  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
SOP  
74LVQ10M  
74LVQ10MTR  
74LVQ10TTR  
TSSOP  
t
t
PHL  
PLH  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 10  
V
technology. It is ideal for low power and low noise  
3.3V applications.  
The internal circuit is composed of 3 stages  
including buffer output, which enables high noise  
immunity and stable output.  
CC  
IMPROVED LATCH-UP IMMUNITY  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74LVQ10 is a low voltage CMOS TRIPLE  
3-INPUT NAND GATE fabricated with sub-micron  
2
silicon gate and double-layer metal wiring C MOS  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/8  

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