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74LVQ08TTR PDF预览

74LVQ08TTR

更新时间: 2024-11-19 21:53:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
11页 217K
描述
QUAD 2-INPUT AND GATE

74LVQ08TTR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-14
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.72
Is Samacsys:N系列:LVQ
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:AND GATE最大I(ol):0.024 A
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):15 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.2 mm
子类别:Gates最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

74LVQ08TTR 数据手册

 浏览型号74LVQ08TTR的Datasheet PDF文件第2页浏览型号74LVQ08TTR的Datasheet PDF文件第3页浏览型号74LVQ08TTR的Datasheet PDF文件第4页浏览型号74LVQ08TTR的Datasheet PDF文件第5页浏览型号74LVQ08TTR的Datasheet PDF文件第6页浏览型号74LVQ08TTR的Datasheet PDF文件第7页 
74LVQ08  
LOW VOLTAGE CMOS QUAD 2-INPUT AND GATE  
HIGH SPEED:  
= 5.6 ns (TYP.) at V = 3.3 V  
t
PD  
CC  
COMPATIBLE WITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
I
= 2µA(MAX.) at T =25°C  
CC  
A
LOW NOISE:  
= 0.3V (TYP.) at V = 3.3V  
75TRANSMISSION LINE DRIVING  
CAPABILITY  
SOP  
TSSOP  
V
OLP  
CC  
Table 1: Order Codes  
PACKAGE  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 12 mA (MIN) at V = 3.0 V  
OH  
OL  
CC  
T & R  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
SOP  
74LVQ08MTR  
74LVQ08TTR  
TSSOP  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 08  
V
technology. It is ideal for low power and low noise  
3.3V applications.  
The internal circuit is composed of 2 stages  
including buffer output, which enables high noise  
immunity and stable output.  
CC  
IMPROVED LATCH-UP IMMUNITY  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74LVQ08 is a low voltage CMOS QUAD  
2-INPUT AND GATE fabricated with sub-micron  
2
silicon gate and double-layer metal wiring C MOS  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 5  
1/11  
July 2004  

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