5秒后页面跳转
74LVCZ161284A PDF预览

74LVCZ161284A

更新时间: 2024-11-18 21:54:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
12页 442K
描述
LOW VOLTAGE HIGH SPEED IEEE 1284 TRANSCEIVER WITH ERROR-FREE POWER-UP

74LVCZ161284A 数据手册

 浏览型号74LVCZ161284A的Datasheet PDF文件第2页浏览型号74LVCZ161284A的Datasheet PDF文件第3页浏览型号74LVCZ161284A的Datasheet PDF文件第4页浏览型号74LVCZ161284A的Datasheet PDF文件第5页浏览型号74LVCZ161284A的Datasheet PDF文件第6页浏览型号74LVCZ161284A的Datasheet PDF文件第7页 
74LVCZ161284A  
LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER  
WITH ERROR-FREE POWER-UP  
I
I
HIGH SPEED: t = 9ns (MAX.) at V = 3V  
PD CC  
LOW POWER DISSIPATION:  
I
=20µA (MAX) at V =3.6V T =85°C  
CC  
CC A  
I
I
I
I
I
I
TTL COMPATIBLE INPUTS  
V =2V (MIN) V =0.8(MAX)  
IH  
IL  
OPERATING VOLTAGE RANGE:  
(OPR) = 3.0V to 3.6V  
TSSOP  
TUBE  
V
CC  
A PORT HAVE STANDARD 4mA TOTEM  
POLE OUTPUT  
B PORT HIGH DRIVE SOURCE/SINK  
CAPABILITY OF 14mA  
AUTO POWER-UP FEATURE TO PREVENT  
PRINTER ERRORS  
SUPPORT IEEE STD 1284-I (LEVEL 1 TYPE)  
AND IEEE STD 1284-II (LEVEL 2 TYPE) FOR  
BIDIRECTIONAL PARALLEL  
ORDER CODES  
PACKAGE  
T & R  
TSSOP  
74LVCZ161284ATTR  
PIN CONNECTION  
COMMUNICATIONS BETWEEN PERSONAL  
COMPUTER ANT PRINTING PERIPHERALS  
TRANSLATION CAPABILITY ALLOW  
OUTPUTS ON CABLE SIDE TO INTERFACE  
WITH 5V SIGNAL  
PULL-UP RESISTOR INTEGRATED ON ALL  
OPEN-DRAIN OUTPUT ELIMINATE THE  
NEED FOR DISCRETE RESISTOR  
REPLACE THE FUNCTION OF TWO  
74LVC1284 DEVICES  
I
I
I
DESCRIPTION  
The 74LVCZ161284A contains eight high speed  
non inverting bidirectional buffers and eleven  
control/status non-inverting buffers with open  
2
drain outputs fabricated in silicon gate C MOS  
technology. It’s intended to provide a standard  
signaling method for  
a bi-direction parallel  
peripheral in an Extended Capabilities Port Mode  
(ECP). The HD (Active HIGH) input pin enables  
the Cable port to switch from Open Drain to a high  
drive totem pole output, capable of sourcing 14mA  
on all thirteen buffer and 84mA on PERI LOGIC  
OUTPUT buffer. The DIR input determines the  
direction of data flow on the bidirectional buffers.  
DIR (Active HIGH) enables data flow from A port  
to B port. DIR (Active LOW) enables data flow  
from B port to A port. The Y output (Y9-Y13) stay  
in the high state after power-on until an associated  
input A9-A13) goes high. When an associated  
input goes high, all Y outputs are active, and non  
July 2005  
1/12  

与74LVCZ161284A相关器件

型号 品牌 获取价格 描述 数据表
74LVCZ161284AGRG4 TI

获取价格

19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP
74LVCZ161284ATTR STMICROELECTRONICS

获取价格

LOW VOLTAGE HIGH SPEED IEEE 1284 TRANSCEIVER WITH ERROR-FREE POWER-UP
74LVCZ16240ADGGRE4 TI

获取价格

LVC/LCX/Z SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48
74LVCZ16244ADGGRE4 TI

获取价格

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
74LVCZ16244ADGGRG4 TI

获取价格

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
74LVCZ16244ADGVRE4 TI

获取价格

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
74LVCZ16244ADGVRG4 TI

获取价格

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
74LVCZ16244ADLRG4 TI

获取价格

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
74LVCZ16245ADGGRE4 TI

获取价格

16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
74LVCZ16245ADGVRE4 TI

获取价格

16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS