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74LVCH244APW PDF预览

74LVCH244APW

更新时间: 2023-09-03 20:29:56
品牌 Logo 应用领域
安世 - NEXPERIA 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
17页 281K
描述
Octal buffer/line driver; 3-stateProduction

74LVCH244APW 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.3控制类型:ENABLE LOW
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TUBE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:7.5 ns传播延迟(tpd):9 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mm

74LVCH244APW 数据手册

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74LVC244A; 74LVCH244A  
Octal buffer/line driver; 3-state  
Rev. 12 — 16 September 2021  
Product data sheet  
1. General description  
The 74LVC244A; 74LVCH244A are 8-bit buffer/line drivers with 3-state outputs. The devices can  
be used as two 4-bit buffers or one 8-bit buffer. Both devices features two output enables (1OE and  
2OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume  
a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature  
allows the use of these devices as translators in mixed 3.3 V and 5 V environments.  
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.  
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry  
disables the output, preventing the potentially damaging backflow current through the device when  
it is powered down.  
2. Features and benefits  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low-power consumption  
Direct interface with TTL levels  
Overvoltage tolerant inputs to 5.5 V  
IOFF circuitry provdes partial Power-down mode operation  
Bus hold on all data inputs (74LVCH244A only)  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

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