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74LVCH16244ABQ PDF预览

74LVCH16244ABQ

更新时间: 2024-11-02 06:31:55
品牌 Logo 应用领域
恩智浦 - NXP 总线驱动器总线收发器逻辑集成电路
页数 文件大小 规格书
19页 176K
描述
16-bit buffer/line driver; 5 V input/output tolerant; 3-state

74LVCH16244ABQ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:4 X 6 MM, 0.55 MM PITCH, PLASTIC, SOT1134-1, HXQFN-60
针数:60Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N系列:LVC/LCX/Z
JESD-30 代码:R-PBCC-B60JESD-609代码:e4
长度:6 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:2位数:4
功能数量:4端口数量:2
端子数量:60最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:HVBCC封装形状:RECTANGULAR
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
传播延迟(tpd):6 ns认证状态:Not Qualified
座面最大高度:0.5 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:BUTT端子节距:0.5 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:40
宽度:4 mmBase Number Matches:1

74LVCH16244ABQ 数据手册

 浏览型号74LVCH16244ABQ的Datasheet PDF文件第2页浏览型号74LVCH16244ABQ的Datasheet PDF文件第3页浏览型号74LVCH16244ABQ的Datasheet PDF文件第4页浏览型号74LVCH16244ABQ的Datasheet PDF文件第5页浏览型号74LVCH16244ABQ的Datasheet PDF文件第6页浏览型号74LVCH16244ABQ的Datasheet PDF文件第7页 
74LVC16244A; 74LVCH16244A  
16-bit buffer/line driver; 5 V input/output tolerant; 3-state  
Rev. 09 — 18 March 2010  
Product data sheet  
1. General description  
The 74LVC16244A; 74LVCH16244A are 16-bit non-inverting buffer/line drivers with  
3-state bus compatible outputs. The device can be used as four 4-bit buffers, two 8-bit  
buffers or one 16-bit buffer. It features four output enable inputs, (1OE to 4OE) each  
controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a  
high-impedance OFF-state.  
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be  
applied to the outputs. These features allow the use of these devices in mixed  
3.3 V and 5 V applications.  
The 74LVCH16244A bus hold on data inputs eliminates the need for external pull-up  
resistors to hold unused inputs.  
2. Features and benefits  
„ 5 V tolerant inputs/outputs for interfacing with 5 V logic  
„ Wide supply voltage range from 1.2 V to 3.6 V  
„ CMOS low power consumption  
„ Multibyte flow-through standard pin-out architecture  
„ Low inductance multiple power and ground pins for minimum noise and ground  
bounce  
„ Direct interface with TTL levels  
„ High-impedance when VCC = 0 V  
„ All data inputs have bus hold. (74LVCH16244A only)  
„ Complies with JEDEC standard JESD8-B / JESD36  
„ ESD protection:  
‹ HBM JESD22-A114F exceeds 2000 V  
‹ MM JESD22-A115-A exceeds 200 V  
„ Specified from 40 °C to +85 °C and 40 °C to +125 °C  

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