Datasheet > 74LVC574APW-Q100

74LVC574APW-Q100

更新时间： 2024-03-03 10:09:40

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
14页	250K
描述
Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-stateProduction

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74LVC574APW-Q100 数据手册

74LVC574A-Q100

Octal D-type flip-flop with 5 V tolerant inputs/outputs;

positive edge-trigger; 3-state

Rev. 1 — 2 November 2023

Product data sheet

1. General description

The 74LVC574A-Q100 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The

device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of

their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH

clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state.

Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either

3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and

5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Wide supply voltage range from 1.2 to 3.6 V

CMOS low power consumption

Direct interface with TTL levels

Overvoltage tolerant inputs to 5.5 V

High-impedance when V_CC= 0 V

8-bit positive edge-triggered register

Independent register and 3-state buffer operation

Flow-through pin-out architecture

I_OFFcircuitry provides partial Power-down mode operation

Complies with JEDEC standard:

•

JESD8-7A (1.65 V to 1.95 V)

JESD8-5A (2.3 V to 2.7 V)

JESD8-C/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

12 3 4 5 6 7...14

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