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74LVC3G16GM

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74LVC3G16GM 数据手册

74LVC3G16

Triple buffer

Rev. 2 — 11 October 2016

Product data sheet

1. General description

The 74LVC3G16 provides three buffers.

The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of

the 74LVC3G16 as a translator in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing a damaging backflow current through the device

when it is powered down.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 5 V tolerant input/output for interfacing with 5 V logic

 High noise immunity

 Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8B/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 24 mA output drive (V_CC= 3.0 V)

 CMOS low power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

12 3 4 5 6 7...15

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型号	品牌	获取价格	描述	数据表
74LVC3G17	NXP	获取价格	Triple non-inverting Schmitt trigger with 5 V tolerant input
74LVC3G17	DIODES	获取价格	Triple gate1 Input Schmitt Trigger Buffer
74LVC3G17DC	NXP	获取价格	Triple non-inverting Schmitt trigger with 5 V tolerant input
74LVC3G17DC	NEXPERIA	获取价格	Triple non-inverting Schmitt trigger with 5 V tolerant inputProduction
74LVC3G17DC,125	NXP	获取价格	74LVC3G17 - Triple non-inverting Schmitt trigger with 5 V tolerant input SSOP 8-Pin
74LVC3G17DC,132	NXP	获取价格	Buffer, LVC/LCX/Z Series, 3-Func, 1-Input, CMOS, PDSO8
74LVC3G17DC-G	NXP	获取价格	Triple non-inverting Schmitt trigger with 5 V tolerant input - Description: Triple Schmitt
74LVC3G17DC-Q100	NXP	获取价格	IC NON-INVERT GATE, Gate
74LVC3G17DC-Q100	NEXPERIA	获取价格	Triple non-inverting Schmitt trigger with 5 V tolerant input
74LVC3G17DP	NXP	获取价格	Triple non-inverting Schmitt trigger with 5 V tolerant input