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74LVC3G06GM PDF预览

74LVC3G06GM

更新时间: 2024-02-26 03:44:20
品牌 Logo 应用领域
恩智浦 - NXP 逻辑集成电路
页数 文件大小 规格书
16页 95K
描述
Triple inverter with open-drain output

74LVC3G06GM 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否无铅: 含铅
是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:unknown风险等级:5.75
Base Number Matches:1

74LVC3G06GM 数据手册

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74LVC3G06  
Triple inverter with open-drain output  
Rev. 07 — 12 March 2009  
Product data sheet  
1. General description  
The 74LVC3G06 provides three inverting buffers.  
The output of this device is an open drain and can be connected to other open-drain  
outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this  
device in a mixed 3.3 V and 5 V environment.  
Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall  
time.  
This device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing a damaging backflow current through the device  
when it is powered down.  
2. Features  
I Wide supply voltage range from 1.65 V to 5.5 V  
I 5 V tolerant input/output for interfacing with 5 V logic  
I High noise immunity  
I Complies with JEDEC standard:  
N JESD8-7 (1.65 V to 1.95 V)  
N JESD8-5 (2.3 V to 2.7 V)  
N JESD8-B/JESD36 (2.7 V to 3.6 V)  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I 24 mA output drive (VCC = 3.0 V)  
I CMOS low power consumption  
I Latch-up performance exceeds 250 mA  
I Direct interface with TTL levels  
I Inputs accept voltages up to 5 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and 40 °C to +125 °C  

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