Datasheet > 74LVC2G86DP

74LVC2G86DP

更新时间： 2024-09-24 11:13:11

品牌	Logo	应用领域
安世 - NEXPERIA		栅光电二极管逻辑集成电路石英晶振触发器
页数	文件大小	规格书
18页	281K
描述
Dual 2-input EXCLUSIVE-OR gateProduction

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74LVC2G86DP 数据手册

74LVC2G86

Dual 2-input EXCLUSIVE-OR gate

Rev. 15 — 21 June 2022

Product data sheet

1. General description

The 74LVC2G86 is a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V

or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V

environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This

device is fully specified for partial power down applications using I_OFF. The I_OFFcircuitry disables

the output, preventing the potentially damaging backflow current through the device when it is

powered down.

2. Features and benefits

•

Wide supply voltage range from 1.65 V to 5.5 V

•

Overvoltage tolerant inputs to 5.5 V

High noise immunity

CMOS low-power dissipation

±24 mA output drive (V_CC= 3.0 V)

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

I_OFFcircuitry provides partial Power-down mode operation

Complies with JEDEC standard:

•

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

JESD36 (4.5 V to 5.5 V)

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

•

Multiple package options

Specified from -40 °C to +85 °C and -40 °C to +125 °C

12 3 4 5 6 7...18

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