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74LVC2G86DC PDF预览

74LVC2G86DC

更新时间: 2024-02-28 17:11:19
品牌 Logo 应用领域
恩智浦 - NXP 栅极触发器逻辑集成电路石英晶振光电二极管
页数 文件大小 规格书
15页 81K
描述
Dual 2-input exclusive-OR gate

74LVC2G86DC 技术参数

生命周期:Active包装说明:HVBCC,
Reach Compliance Code:compliantFactory Lead Time:13 weeks
风险等级:1.59系列:LVC/LCX/Z
JESD-30 代码:R-PBCC-B8长度:1.35 mm
逻辑集成电路类型:XOR GATE功能数量:2
输入次数:2端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HVBCC
封装形状:RECTANGULAR封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):12.4 ns
座面最大高度:0.35 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:BUTT
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:0.8 mm

74LVC2G86DC 数据手册

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74LVC2G86  
Dual 2-input exclusive-OR gate  
Rev. 03 — 7 February 2005  
Product data sheet  
1. General description  
The 74LVC2G86 is a high-performance, low-power, low-voltage, Si-gate CMOS device  
and superior to most advanced CMOS compatible TTL families.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this  
devices as translators in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry  
disables the output, preventing the damaging backflow current through the device when it  
is powered down.  
The 74LVC2G86 provides the dual 2-input exclusive-OR gate.  
2. Features  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant inputs for interfacing with 5 V logic  
Inputs accept voltages up to 5 V  
Direct interface with TTL levels  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V)  
±24 mA output drive (VCC = 3.0 V)  
CMOS low-power consumption  
Latch-up performance exceeds 250 mA  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C  

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