74LVC2G07
Buffers with open-drain outputs
Rev. 13 — 16 August 2023
Product data sheet
1. General description
The 74LVC2G07 is a dual buffer with open-drain outputs. Inputs can be driven from either 3.3 V
or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V
environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and
fall times. This device is fully specified for partial power down applications using IOFF. The IOFF
circuitry disables the output, preventing the potentially damaging backflow current through the
device when it is powered down.
2. Features and benefits
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Wide supply voltage range from 1.65 V to 5.5 V
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Overvoltage tolerant inputs to 5.5 V
High noise immunity
-24 mA output drive (VCC = 3.0 V)
CMOS low power dissipation
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
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JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
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ESD protection:
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HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
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Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C