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74LVC257AD-T PDF预览

74LVC257AD-T

更新时间: 2024-02-05 19:47:06
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
18页 187K
描述
IC LVC/LCX/Z SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16, PLASTIC, SO-16, Multiplexer/Demultiplexer

74LVC257AD-T 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.08系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm逻辑集成电路类型:MULTIPLEXER
湿度敏感等级:1功能数量:4
输入次数:2输出次数:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):7 ns认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

74LVC257AD-T 数据手册

 浏览型号74LVC257AD-T的Datasheet PDF文件第2页浏览型号74LVC257AD-T的Datasheet PDF文件第3页浏览型号74LVC257AD-T的Datasheet PDF文件第4页浏览型号74LVC257AD-T的Datasheet PDF文件第5页浏览型号74LVC257AD-T的Datasheet PDF文件第6页浏览型号74LVC257AD-T的Datasheet PDF文件第7页 
74LVC257A  
Quad 2-input multiplexer with 5 V tolerant inputs/outputs;  
3-state  
Rev. 6 — 28 November 2011  
Product data sheet  
1. General description  
The 74LVC257A is a quad 2-input multiplexer with 3-state outputs, which select 4 bits of  
data from two sources and are controlled by a common data select input (pin S). The data  
inputs from source 0 (pins 1I0 to 4I0) are selected when pin S is LOW and the data inputs  
from source 1 (pins 1I1 to 4I1) are selected when pin S is HIGH. Data appears at the  
outputs (pins 1Y to 4Y) in true (non-inverting) form from the selected inputs. The device is  
the logic implementation of a 4-pole, 2-position switch, where the position of the switch is  
determined by the logic levels applied to pin S. The outputs are forced to a  
high-impedance OFF-state when pin OE is HIGH.  
Inputs can be driven from either 3.3 V or 5.0 V devices. When disabled, up to 5.5 V can be  
applied to the outputs. These features allow the use of these devices as translators in  
mixed 3.3 V and 5 V applications.  
2. Features and benefits  
5 V tolerant inputs/outputs, for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low-power consumption  
Direct interface with TTL levels  
Output drive capability 50 transmission lines at 85 C  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Specified from 40 C to +85 C and 40 C to +125 C  
 
 

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