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74LVC1T45GM PDF预览

74LVC1T45GM

更新时间: 2024-01-10 11:06:19
品牌 Logo 应用领域
恩智浦 - NXP 总线驱动器总线收发器
页数 文件大小 规格书
30页 632K
描述
Dual supply translating transceiver; 3-state

74LVC1T45GM 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOT-363
包装说明:PLASTIC, SOT-363, SC-88, 6 PIN针数:6
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.54Is Samacsys:N
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G6
JESD-609代码:e3长度:2 mm
逻辑集成电路类型:BUS TRANSCEIVER湿度敏感等级:1
位数:1功能数量:1
端口数量:2端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):23.5 ns
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.2 V
标称供电电压 (Vsup):1.5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:PURE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:1.25 mm
Base Number Matches:1

74LVC1T45GM 数据手册

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74LVC1T45; 74LVCH1T45  
Dual supply translating transceiver; 3-state  
Rev. 02 — 19 January 2010  
Product data sheet  
1. General description  
The 74LVC1T45; 74LVCH1T45 are single bit, dual supply transceivers with 3-state outputs  
that enables bidirectional level translation. They feature one data input-output port (A and  
B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A)  
and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making the device  
suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V,  
3.3 V and 5.0 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to  
V
CC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows  
transmission from B to A.  
The devices are fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing any damaging backflow current through the  
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at  
GND level, both A port and B port are in the high-impedance OFF-state.  
Active bus hold circuitry in the 74LVCH1T45 holds unused or floating data inputs at a valid  
logic level.  
2. Features  
„ Wide supply voltage range:  
‹ VCC(A): 1.2 V to 5.5 V  
‹ VCC(B): 1.2 V to 5.5 V  
„ High noise immunity  
„ Complies with JEDEC standards:  
‹ JESD8-7 (1.2 V to 1.95 V)  
‹ JESD8-5 (1.8 V to 2.7 V)  
‹ JESD8C (2.7 V to 3.6 V)  
‹ JESD36 (4.5 V to 5.5 V)  
„ ESD protection:  
‹ HBM JESD22-A114E Class 3A exceeds 4000 V  
‹ CDM JESD22-C101C exceeds 1000 V  
„ Maximum data rates:  
‹ 420 Mbps (3.3 V to 5.0 V translation)  
‹ 210 Mbps (translate to 3.3 V))  
‹ 140 Mbps (translate to 2.5 V)  
‹ 75 Mbps (translate to 1.8 V)  
‹ 60 Mbps (translate to 1.5 V)  
„ Suspend mode  

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