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74LVC1G32 PDF预览

74LVC1G32

更新时间: 2024-11-21 05:05:51
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
14页 80K
描述
Single 2-input OR gate

74LVC1G32 数据手册

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74LVC1G32  
Single 2-input OR gate  
Rev. 06 — 2 August 2007  
Product data sheet  
1. General description  
The 74LVC1G32 provides one 2-input OR function.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these  
devices as translators in mixed 3.3 V and 5 V applications.  
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall  
time.  
This device is fully specified for partial power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
2. Features  
Wide supply voltage range from 1.65 V to 5.5 V  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V)  
±24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
ESD protection:  
HBM JESD22-A114E exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C  

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增强型产品单路 3 输入正或与门 | DBV | 6 | -55 to 125