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74LVC1G132DBVTE4 PDF预览

74LVC1G132DBVTE4

更新时间： 2024-11-17 05:05:51
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德州仪器 - TI 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
15页 468K
描述
SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

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74LVC1G132DBVTE4 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOT-23
包装说明：LSSOP, TSOP5/6,.11,37针数：5
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.36系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G5长度：2.9 mm
负载电容（CL）：50 pF逻辑集成电路类型：NAND GATE
最大I（ol）：0.024 A功能数量：1
输入次数：2端子数量：5
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LSSOP封装等效代码：TSOP5/6,.11,37
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 VProp。Delay @ Nom-Sup：6 ns
传播延迟（tpd）：16 ns认证状态：Not Qualified
施密特触发器：YES座面最大高度：1.45 mm
子类别：Gates最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子形式：GULL WING
端子节距：0.95 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：1.6 mm
Base Number Matches：1

74LVC1G132DBVTE4 数据手册

 浏览型号74LVC1G132DBVTE4的Datasheet PDF文件第2页浏览型号74LVC1G132DBVTE4的Datasheet PDF文件第3页浏览型号74LVC1G132DBVTE4的Datasheet PDF文件第4页浏览型号74LVC1G132DBVTE4的Datasheet PDF文件第5页浏览型号74LVC1G132DBVTE4的Datasheet PDF文件第6页浏览型号74LVC1G132DBVTE4的Datasheet PDF文件第7页 
SN74LVC1G132  
SINGLE 2-INPUT NAND GATE  
WITH SCHMITT-TRIGGER INPUTS  
www.ti.com  
SCES546B–FEBRUARY 2004–REVISED SEPTEMBER 2006  
FEATURES  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
•
Available in Texas Instruments NanoStar™  
and NanoFree™ Packages  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
•
•
•
•
Supports 5-V VCC Operation  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Inputs Accept Voltages to 5.5 V  
Max tpd of 5.3 ns at 3.3 V  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
– 1000-V Charged-Device Model (C101)  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
3
2
1
4
5
GND  
B
Y
VCC  
1
2
3
5
A
B
VCC  
1
2
3
5
4
A
B
VCC  
A
4
GND  
Y
GND  
Y
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVC1G132 contains one 2-input NAND gate with Schmitt-trigger inputs designed for 1.65-V to 5.5-V  
VCC operation and performs the Boolean function Y = A • B or Y = A + B in positive logic.  
Because of Schmitt action, this device has different input threshold levels for positive-going (VT+) and  
negative-going (VT–) signals.  
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
SN74LVC1G132YEPR  
Reel of 3000  
_ _ _D5_  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP  
(Pb-free)  
SN74LVC1G132YZPR  
–40°C to 85°C  
Reel of 3000  
Reel of 250  
Reel of 3000  
Reel of 250  
SN74LVC1G132DBVR  
SN74LVC1G132DBVT  
SN74LVC1G132DCKR  
SN74LVC1G132DCKT  
SOT (SOT-23) – DBV  
SOT (SC-70) – DCK  
C3B_  
D5_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...15

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74LVC1G132DBVTE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC1G132DBVTG4 TI

完全替代

 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SN74LVC1G132DBVT TI

完全替代

 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
SN74LVC1G132DBVR TI

完全替代

 SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

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