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74LVC1G126DCKTE4 PDF预览

74LVC1G126DCKTE4

更新时间： 2024-09-16 05:05:51
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
18页 471K
描述
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

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74LVC1G126DCKTE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：TSSOP, TSSOP5/6,.08针数：5
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.04控制类型：ENABLE HIGH
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G5
JESD-609代码：e4长度：2 mm
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
湿度敏感等级：1位数：1
功能数量：1端口数量：2
端子数量：5最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP5/6,.08
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：4.5 ns
传播延迟（tpd）：8 ns认证状态：Not Qualified
座面最大高度：1.1 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：1.25 mm
Base Number Matches：1

74LVC1G126DCKTE4 数据手册

 浏览型号74LVC1G126DCKTE4的Datasheet PDF文件第2页浏览型号74LVC1G126DCKTE4的Datasheet PDF文件第3页浏览型号74LVC1G126DCKTE4的Datasheet PDF文件第4页浏览型号74LVC1G126DCKTE4的Datasheet PDF文件第5页浏览型号74LVC1G126DCKTE4的Datasheet PDF文件第6页浏览型号74LVC1G126DCKTE4的Datasheet PDF文件第7页 
SN74LVC1G126  
SINGLE BUS BUFFER GATE  
WITH 3-STATE OUTPUT  
www.ti.com  
SCES224N–APRIL 1999–REVISED FEBRUARY 2007  
FEATURES  
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
•
•
•
•
•
Supports 5-V VCC Operation  
ESD Protection Exceeds JESD 22  
Inputs Accept Voltages to 5.5 V  
Max tpd of 3.7 ns at 3.3 V  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
1000-V Charged-Device Model (C101)  
Ioff Supports Partial-Power-Down Mode  
Operation  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
1
2
3
5
4
OE  
A
VCC  
Y
1
2
3
5
OE  
A
VCC  
1
2
3
OE  
A
5
4
VCC  
GND  
4
GND  
Y
GND  
Y
YZP PACKAGE  
(BOTTOM VIEW)  
DRY PACKAGE  
(TOP VIEW)  
3
2
1
4
GND  
A
Y
1
2
3
6
5
4
OE  
A
VCC  
NC  
Y
5
OE  
VCC  
GND  
NC – No internal connection  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This single bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.  
The SN74LVC1G126 is a single line driver with a 3-state output. The output is disabled when the output-enable  
(OE) input is low.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the  
driver.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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