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74LVC1G08GN PDF预览

74LVC1G08GN

更新时间: 2024-01-15 15:53:32
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
19页 354K
描述
Single 2-input AND gate

74LVC1G08GN 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否无铅: 含铅
是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
风险等级:5.28系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G5长度:2.05 mm
逻辑集成电路类型:AND GATE功能数量:1
输入次数:2端子数量:5
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):10.5 ns
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.25 mm

74LVC1G08GN 数据手册

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74LVC1G08  
Single 2-input AND gate  
Rev. 10 — 29 June 2012  
Product data sheet  
1. General description  
The 74LVC1G08 provides one 2-input AND function.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these  
devices as translators in mixed 3.3 V and 5 V applications.  
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall  
time.  
This device is fully specified for partial power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
2. Features and benefits  
Wide supply voltage range from 1.65 V to 5.5 V  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V)  
24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C  

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