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74LVC169BQ PDF预览

74LVC169BQ

更新时间： 2024-09-14 06:31:55
品牌 Logo 应用领域
恩智浦 - NXP 计数器触发器逻辑集成电路
页数 文件大小 规格书
22页 131K
描述
Presettable synchronous 4-bit up/down binary counter

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中文翻译

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74LVC169BQ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFN
包装说明：2.50 X 3.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-763-1, DHVQFN-16针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.83Is Samacsys：N
计数方向：BIDIRECTIONAL系列：LVC/LCX/Z
JESD-30 代码：R-PQCC-N16JESD-609代码：e4
长度：3.5 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：150000000 Hz最大I（ol）：0.024 A
工作模式：SYNCHRONOUS湿度敏感等级：1
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC16,.1X.14,20
封装形状：RECTANGULAR封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 V传播延迟（tpd）：11 ns
认证状态：Not Qualified座面最大高度：1 mm
子类别：Counters最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.2 V标称供电电压 (Vsup)：2.7 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
触发器类型：POSITIVE EDGE宽度：2.5 mm
最小 fmax：150 MHzBase Number Matches：1

74LVC169BQ 数据手册

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74LVC169  
Presettable synchronous 4-bit up/down binary counter  
Rev. 05 — 8 June 2009  
Product data sheet  
1. General description  
The 74LVC169 is a synchronous presettable 4-bit binary counter which features an  
internal look-ahead carry circuitry for cascading in high-speed counting applications.  
Synchronous operation is provided by having all flip-flops clocked simultaneously so that  
the outputs (pins Q0 to Q3) change simultaneously with each other when so instructed by  
the count-enable (pins CEP and CET) inputs and internal gating. This mode of operation  
eliminates the output counting spikes that are normally associated with asynchronous  
(ripple clock) counters. A buffered clock (pin CP) input triggers the four flip-flops on the  
LOW-to-HIGH transition of the clock.  
The counter is fully programmable; that is, the outputs may be preset to any number  
between 0 and its maximum count. Presetting is synchronous with the clock and takes  
place regardless of the levels of the count enable inputs. A LOW level on the parallel  
enable (pin PE) input disables the counter and causes the data at the Dn input to be  
loaded into the counter on the next LOW-to-HIGH transition of the clock. The direction of  
the counting is controlled by the up/down (pin U/D) input. When pin U/D is HIGH, the  
counter counts up, when LOW, it counts down.  
The look-ahead carry circuitry is provided for cascading counters for n-bit synchronous  
applications without additional gating. Instrumental in accomplishing this function are two  
count-enable (pins CEP and CET) inputs and a terminal count (pin TC) output. Both  
count-enable (pins CEP and CET) inputs must be LOW to count. Input pin CET is fed  
forward to enable the terminal count (pin TC) output. Pin TC thus enabled will produce a  
LOW-level output pulse with a duration approximately equal to a HIGH level portion of  
pin Q0 output. The LOW level pin TC pulse is used to enable successive cascaded  
stages.  
The 74LVC169 uses edge triggered J-K type flip-flops and has no constraints on changing  
the control of data input signals in either state of the clock. The only requirement is that  
the various inputs attain the desired state at least a set-up time before the next  
LOW-to-HIGH transition of the clock and remain valid for the recommended hold time  
thereafter.  
The parallel load operation takes precedence over the other operations, as indicated in  
the mode select table. When pin PE is LOW, the data on the input pins D0 to D3 enters  
the flip-flops on the next LOW-to-HIGH transition of the clock.  
1234567...22

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