Datasheet > 逻辑 > 栅极> 74LVC14ABQ

74LVC14ABQ

更新时间： 2024-09-23 11:51:47

品牌	Logo	应用领域
恩智浦 - NXP		触发器逻辑集成电路栅
页数	文件大小	规格书
26页	137K
描述
Hex inverting Schmitt trigger with 5 V tolerant input

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74LVC14ABQ 数据手册

74LVC1G99

Ultra-conﬁgurable multiple function gate; 3-state

Rev. 01 — 3 January 2008

Product data sheet

1. General description

The 74LVC1G99 provides a low voltage, ultra-conﬁgurable, multiple function gate with

3-state output. The device can be conﬁgured as one of several logic functions including,

AND, OR, NAND, NOR, XOR, XNOR, inverter, buffer and MUX. No external components

are required to conﬁgure the device as all inputs can be connected directly to V_CCor GND.

The 3-state output is controlled by the output enable input (OE). A HIGH level at OE

causes the output (Y) to assume a high-impedance OFF-state. When OE is LOW, the

output state is determined by the signals applied to the Schmitt-trigger inputs (A, B, C and

D).

Due to the use of Schmitt-trigger inputs the device is tolerant of slowly changing input

signals, transforming them into sharply deﬁned, jitter free output signals. By eliminating

leakage current paths to V_CCand GND, the inputs and disabled output are also

over-voltage tolerant, making the device suitable for mixed-voltage applications.

This device is fully speciﬁed for partial power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backﬂow current through

the device when it is powered down.

The 74LVC1G99 is fully speciﬁed over the supply range from 1.65 V to 5.5 V.

2. Features

I Wide supply voltage range from 1.65 V to 5.5 V

I 5 V tolerant inputs for interfacing with 5 V logic

I High noise immunity

I Complies with JEDEC standard:

N JESD8-7 (1.65 V to 1.95 V)

N JESD8-5 (2.3 V to 2.7 V)

N JESD8-B/JESD36 (2.7 V to 3.6 V)

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

I ±24 mA output drive (V_CC= 3.0 V)

I CMOS low power consumption

I Latch-up performance exceeds 250 mA

I Direct interface with TTL levels

I Inputs accept voltages up to 5 V

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C.

12 3 4 5 6 7...26

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74LVC14ABQ 替代型号

型号	品牌	替代类型	描述	数据表
SN74LVC14ARGYR	TI	功能相似	HEX SCHMITT-TRIGGER INVERTERS
SN74LVC14ARGYRG4	TI	功能相似	HEX SCHMITT-TRIGGER INVERTERS

与74LVC14ABQ相关器件

型号	品牌	获取价格	描述	数据表
74LVC14ABQ-Q100	NEXPERIA	获取价格	Hex inverting Schmitt trigger with 5 V tolerant input
74LVC14ABZ	NEXPERIA	获取价格	Hex inverting Schmitt trigger with 5 V tolerant inputProduction
74LVC14AD	ADI	获取价格	ADSP-BF506F EZ-KIT Lite® Evaluation System Ma
74LVC14AD	NXP	获取价格	Hex inverting Schmitt-trigger with 5V tolerant input
74LVC14AD	NEXPERIA	获取价格	Hex inverting Schmitt trigger with 5 V tolerant inputProduction
74LVC14AD,112	NXP	获取价格	74LVC14A - Hex inverting Schmitt trigger with 5 V tolerant input SOIC 14-Pin
74LVC14AD,118	NXP	获取价格	74LVC14A - Hex inverting Schmitt trigger with 5 V tolerant input SOIC 14-Pin
74LVC14ADB	NXP	获取价格	Hex inverting Schmitt-trigger with 5V tolerant input
74LVC14ADB,112	NXP	获取价格	74LVC14A - Hex inverting Schmitt trigger with 5 V tolerant input SSOP1 14-Pin
74LVC14ADB,118	NXP	获取价格	74LVC14A - Hex inverting Schmitt trigger with 5 V tolerant input SSOP1 14-Pin

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