74LV4020DB

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74LV4020DB 数据手册

74LV4020

14-stage binary ripple counter

Rev. 01 — 29 November 2005

Product data sheet

1. General description

The 74LV4020 is a low-voltage Si-gate CMOS device and is pin and function compatible

with the 74HC4020 and 74HCT4020.

The 74LV4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding

asynchronous master reset input (MR) and 12 fully buffered parallel outputs (Q0, and

Q3 to Q13).

The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all

counter stages and forces all outputs LOW, independent of the state of CP.

Each counter stage is a static toggle ﬂip-ﬂop.

2. Features

■ Optimized for low-voltage applications: 1.0 V to 5.5 V

■ Accepts TTL input levels between V_CC= 2.7 V and V_CC= 3.6 V

■ Typical LOW-level output voltage (peak) or output ground bounce: V_OL(p)< 0.8 V at

V_CC= 3.3 V and T_amb= 25 °C

■ Typical HIGH-level output voltage (valley) or output V_OHundershoot: V_OH(v)> 2 V at

V_CC= 3.3 V and T_amb= 25 °C

■ ESD protection:

◆ HBM EIA/JESD22-A114-C exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V.

■ Multiple package options

■ Speciﬁed from −40 °C to +80 °C and from −40 °C to +125 °C.

3. Applications

■ Frequency dividing circuits

■ Time delay circuits

■ Control counters

12 3 4 5 6 7...20

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型号	品牌	获取价格	描述	数据表
74LV4020DB,112	NXP	获取价格	74LV4020 - 14-stage binary ripple counter SSOP1 16-Pin
74LV4020DB,118	NXP	获取价格	74LV4020 - 14-stage binary ripple counter SSOP1 16-Pin
74LV4020DB-T	ETC	获取价格	Asynchronous Up Counter
74LV4020D-T	ETC	获取价格	Asynchronous Up Counter
74LV4020N	NXP	获取价格	14-stage binary ripple counter
74LV4020PW	NXP	获取价格	14-stage binary ripple counter
74LV4020PW,112	NXP	获取价格	74LV4020 - 14-stage binary ripple counter TSSOP 16-Pin
74LV4020PWDH	NXP	获取价格	IC LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16, PL
74LV4020PWDH-T	NXP	获取价格	IC LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16, PL
74LV4020PW-T	ETC	获取价格	Asynchronous Up Counter