Datasheet > 74LV32APW

74LV32APW

更新时间： 2024-09-27 14:52:55

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
10页	187K
描述
Quad 2-input OR gateProduction

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74LV32APW 数据手册

74LV32A

Quad 2-input OR gate

Rev. 1 — 19 December 2018

Product data sheet

1. General description

The 74LV32A is a quad 2-input OR gate.

Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed

voltage environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

•

Wide supply voltage range from 2.0 V to 5.5 V

•

Maximum t_pdof 9.5 ns at 5 V

Typical V_OL(p)< 0.8 V at V_CC= 3.3 V, T_amb= 25 °C

Typical V_OH(v)> 2.3 V at V_CC= 3.3 V, T_amb= 25 °C

Supports mixed-mode voltage operation on all ports

I_OFFcircuitry provides partial Power-down mode operation

Latch-up performance exceeds 250 mA per JESD 78 Class II

ESD protection:

•

MM: MM JESD22-A115-B exceeds 200 V

HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4 kV

CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 2 kV

•

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LV32APW

-40 °C to +125 °C

TSSOP14

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

12 3 4 5 6 7...10

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