Datasheet > 74LV165A-Q100

74LV165A-Q100

更新时间： 2024-09-24 01:12:31

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
19页	779K
描述
8-bit parallel-in/serial-out shift register

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74LV165A-Q100 数据手册

74LV165A-Q100

8-bit parallel-in/serial-out shift register

Rev. 3 — 28 March 2014

Product data sheet

1. General description

The 74LV165A-Q100 is an 8-bit parallel-load or serial-in shift register with complementary

serial outputs (Q7 and Q7) available from the last stage. When the parallel-load input (PL)

is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously.

When input PL is HIGH, data enters the register serially at the input DS. It shifts one place

to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature

allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the

succeeding stage. The clock input is a gate-OR structure which allows one input to be

used as an active LOW clock enable input (CE) input. The pin assignment for the inputs

CP and CE is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH

transition of the input CE should only take place while CP HIGH for predictable operation.

Schmitt-trigger action at all inputs, makes the circuit tolerant for slower input rise and fall

times. It is fully specified for partial-power-down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the damaging current backflow through the device when it

is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 3) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 3)

 Specified from 40 C to +85 C

 Wide supply voltage range from 2.0 V to 5.5 V

 Synchronous parallel-to-serial applications

 Synchronous serial input for easy expansion

 Latch-up performance exceeds 250 mA

 CMOS LOW power consumption

 5.5 V tolerant inputs/outputs

 Direct interface with TTL levels (2.7 V to 3.6 V)

 Power-down mode

 Complies with JEDEC standards:

 JESD8-5 (2.3 V to 2.7 V)

 JESD8B/JESD36 (2.7 V to 3.6 V)

 JESD8-1A (4.5 V to 5.5 V)

 ESD protection:

 MIL-STD-833, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

12 3 4 5 6 7...19

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