Datasheet > 74LV123PW-Q100

74LV123PW-Q100

更新时间： 2024-11-26 17:00:39

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
18页	288K
描述
Dual retriggerable monostable multivibrator with resetProduction

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74LV123PW-Q100 数据手册

74LV123-Q100

Dual retriggerable monostable multivibrator with reset

Rev. 1 — 15 January 2024

Product data sheet

1. General description

The 74LV123-Q100 is a dual retriggerable monostable multivibrator with reset. The basic output

pulse width is programmed by selection of external components (R_EXTand C_EXT). Once triggered

this basic pulse width may be extended by retriggering either of the edge triggered inputs (nA or

(nB). By repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as

long as desired. Alternatively, an output delay can be terminated at any time by a LOW-going edge

on input nRD. Control inputs include clamp diodes. This enables the use of current limiting resistors

to interface inputs to voltages in excess V_CC. Schmitt-trigger action at nA and nB inputs makes the

circuit tolerant of slower input rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Wide supply voltage range from 1.0 V to 5.5 V

CMOS low power dissipation

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

Optimized for low-voltage applications: 1.0 V to 3.6 V

Accepts TTL input levels between V_CC= 2.7 V and V_CC= 3.6 V

Typical output ground bounce: < 0.8 V at V_CC= 3.3 V and T_amb= 25 °C

Typical HIGH-level output voltage (V_OH) undershoot: > 2 V at V_CC= 3.3 V and T_amb= 25 °C

DC triggered from active HIGH or active LOW inputs

Retriggerable for very long pulses up to 100 % duty factor

Direct reset terminates output pulses

Schmitt-trigger action on all inputs except for the reset input

Complies with JEDEC standards:

•

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

JESD36 (4.5 V to 5.5 V)

•

ESD protection:

•

HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

Multiple package options

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LV123D-Q100

-40 °C to +125 °C

SO16

plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

12 3 4 5 6 7...18

中文翻译

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与74LV123PW-Q100相关器件

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74LV123PW-T	ETC	获取价格	Monostable Multivibrator
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74LV125A	TI	获取价格	QUADRUPLE BUS BUFFER GATES
74LV125D	NXP	获取价格	Quad buffer/line driver 3-State
74LV125D,112	NXP	获取价格	74LV125 - Quad buffer/line driver; 3-state SOIC 14-Pin
74LV125D,118	NXP	获取价格	74LV125 - Quad buffer/line driver; 3-state SOIC 14-Pin
74LV125DB	NXP	获取价格	Quad buffer/line driver 3-State
74LV125DB,112	NXP	获取价格	74LV125 - Quad buffer/line driver; 3-state SSOP1 14-Pin
74LV125DB,118	NXP	获取价格	74LV125 - Quad buffer/line driver; 3-state SSOP1 14-Pin
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