SN54/74LS90
SN54/74LS92
SN54/74LS93
DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
The SN54/74LS90, SN54/74LS92 and SN54/74LS93 are high-speed
4-bit ripple type counters partitioned into two sections. Each counter has a di-
vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or
divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi-
tion on the clock inputs. Each section can be used separately or tied together
(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of
the counters have a 2-input gated Master Reset (Clear), and the LS90 also
has a 2-input gated Master Set (Preset 9).
LOW POWER SCHOTTKY
• Low Power Consumption . . . Typically 45 mW
• High Count Rates . . . Typically 42 MHz
• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,
Binary
J SUFFIX
CERAMIC
CASE 632-08
14
1
• Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES
LOADING (Note a)
N SUFFIX
HIGH
LOW
PLASTIC
CASE 646-06
CP
CP
CP
Clock (Active LOW going edge) Input to
÷2 Section
0.5 U.L.
1.5 U.L.
0
1
1
14
1
Clock (Active LOW going edge) Input to
÷5 Section (LS90), ÷6 Section (LS92)
0.5 U.L.
0.5 U.L.
2.0 U.L.
1.0 U.L.
Clock (Active LOW going edge) Input to
÷8 Section (LS93)
D SUFFIX
SOIC
CASE 751A-02
MR , MR
1
MS , MS
Master Reset (Clear) Inputs
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
2
2
14
Master Set (Preset-9, LS90) Inputs
Output from ÷2 Section (Notes b & c)
Outputs from ÷5 (LS90), ÷6 (LS92),
÷8 (LS93) Sections (Note b)
1
1
Q
0
Q , Q , Q
1 3
2
ORDERING INFORMATION
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)
b. Temperature Ranges.
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
c. The Q Outputs are guaranteed to drive the full fan-out plus the CP input of the device.
0
1
d. To insure proper operation the rise (t ) and fall time (t ) of the clock must be less than 100 ns.
r
f
LOGIC SYMBOL
LS92
LS90
LS93
6
1
7
2
MS
14
1
CP
CP
14
1
CP
0
14
1
CP
CP
0
0
CP
1
1
1
MR
Q Q Q Q
0 1 2 3
MR
Q Q Q Q
0 1 2 3
MR
Q Q Q Q
0 1 2 3
1 2
1
2
7
1
2
2
3
12
9
8 11
2
3
12
9
8
11
6
12 11
= PIN 5
9
8
V
= PIN 5
V
V
= PIN 5
CC
CC
GND = PIN 10
NC = PINS 2, 3, 4, 13
CC
GND = PIN 10
NC = PIN 4, 6, 7, 13
GND = PIN 10
NC = PINS 4, 13
FAST AND LS TTL DATA
5-1