74LS90DCQR

更新时间： 2024-11-18 13:04:59

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		计数器
页数	文件大小	规格书
6页	64K
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数据手册

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74LS90DCQR 数据手册

August 1986

Revised March 2000

DM74LS90

Decade and Binary Counters

General Description

Features

Each of these monolithic counters contains four master-

slave flip-flops and additional gating to provide a divide-by-

two counter and a three-stage binary counter for which the

count cycle length is divide-by-five for the DM74LS90.

■ Typical power dissipation 45 mW

■ Count frequency 42 MHz

All of these counters have a gated zero reset and the

DM74LS90 also has gated set-to-nine inputs for use in

BCD nine’s complement applications.

To use their maximum count length (decade or four bit

binary), the B input is connected to the Q_Aoutput. The

input count pulses are applied to input A and the outputs

are as described in the appropriate truth table. A symmetri-

cal divide-by-ten count can be obtained from the

DM74LS90 counters by connecting the Q_Doutput to the A

input and applying the input count to the B input which

gives a divide-by-ten square wave at output Q_A.

Ordering Code:

Order Number Package Number

Package Description

DM74LS90M

DM74LS90N

M14A

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Reset/Count Truth Table

Reset Inputs

Output

R0(1)

R0(2)

R9(1)

R9(2) Q_DQ_CQ_BQ_A

COUNT

DS006381

www.fairchildsemi.com

12 3 4 5 6

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与74LS90DCQR相关器件

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