Datasheet > 74LS73

74LS73

更新时间： 2024-11-20 22:53:19

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器
页数	文件大小	规格书
3页	78K
描述
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

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数据手册

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74LS73 数据手册

SN54/74LS73A

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

The SN54LS/74LS73A offers individual J, K, clear, and clock inputs. These

dual flip-flops are designed so that when the clock goes HIGH, the inputs are

enabled and data will be accepted. The logic level of the J and K inputs may

be allowed to change when the clock pulse is HIGH and the bistable will per-

form according to the truth table as long as minimum set-up times are ob-

served. Input data is transferred to the outputs on the negative-going edge of

the clock pulse.

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

LOW POWER SCHOTTKY

LOGIC DIAGRAM (Each Flip-Flop)

J SUFFIX

CERAMIC

CASE 632-08

13 (8)

12 (9)

N SUFFIX

PLASTIC

CASE 646-06

CLEAR

2 (6)

3 (10)

14 (7)

1 (15)

CLOCK (CP)

D SUFFIX

SOIC

CASE 751A-02

ORDERING INFORMATION

SN54LSXXJ

SN74LSXXN

SN74LSXXD

Ceramic

Plastic

SOIC

MODE SELECT — TRUTH TABLE

INPUTS

OUTPUTS

OPERATING MODE

LOGIC SYMBOL

Reset (Clear)

Toggle

Load “0” (Reset)

Load “1” (Set)

Hold

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Don’t Care

l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time

l, h (q) = prior to the HIGH to LOW clock transition.

= PIN 4

GND = PIN 11

FAST AND LS TTL DATA

5-68

12 3

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与74LS73相关器件

型号	品牌	获取价格	描述	数据表
74LS73A	FAIRCHILD	获取价格	Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outp
74LS73A	NXP	获取价格	IC LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, FF
74LS73A	HITACHI	获取价格	Dual J-K Flip-Flops(with Clear)
74LS73A	TI	获取价格	DUAL J-K FLIP-FLOPS WITH CLEAR
74LS73F	NXP	获取价格	IC LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, FF
74LS73FC	FAIRCHILD	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDFP14,
74LS73FCQM	FAIRCHILD	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDFP14,
74LS73FCQR	FAIRCHILD	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDFP14,
74LS73N	NXP	获取价格	IC LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, PL
74LS73NA+1	RAYTHEON	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, PDIP14,