74LS73

更新时间： 2024-11-08 22:53:19

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
5页	56K
描述
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

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数据手册

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74LS73 数据手册

August 1986

Revised March 2000

DM74LS73A

Dual Negative-Edge-Triggered Master-Slave

J-K Flip-Flops with Clear and Complementary Outputs

General Description

This device contains two independent negative-edge-trig-

gered J-K flip-flops with complementary outputs. The J and

K data is processed by the flip-flops on the falling edge of

the clock pulse. The clock triggering occurs at a voltage

level and is not directly related to the transition time of the

negative going edge of the clock pulse. The data on the J

and K inputs is allowed to change while the clock is HIGH

or LOW without affecting the outputs as long as setup and

hold times are not violated. A low logic level on the clear

input will reset the outputs regardless of the levels of the

other inputs.

Ordering Code:

Order Number Package Number

Package Description

DM74LS73AM

DM74LS73AN

M14A

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

CLK

Outputs

CLR

↓

Q₀

Toggle

Q₀

H = HIGH Logic Level

L = LOW Logic Level

X = Either LOW or HIGH Logic Level

↓ = Negative going edge of pulse.

= The output logic level before the indicated input conditions were

established.

Toggle = Each output changes to the complement of its previous level on

each falling edge of the clock pulse.

DS006372

www.fairchildsemi.com

12 3 4 5

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与74LS73相关器件

型号	品牌	获取价格	描述	数据表
74LS73A	FAIRCHILD	获取价格	Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outp
74LS73A	NXP	获取价格	IC LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, FF
74LS73A	HITACHI	获取价格	Dual J-K Flip-Flops(with Clear)
74LS73A	TI	获取价格	DUAL J-K FLIP-FLOPS WITH CLEAR
74LS73F	NXP	获取价格	IC LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, FF
74LS73FC	FAIRCHILD	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDFP14,
74LS73FCQM	FAIRCHILD	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDFP14,
74LS73FCQR	FAIRCHILD	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDFP14,
74LS73N	NXP	获取价格	IC LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, PL
74LS73NA+1	RAYTHEON	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, PDIP14,