5秒后页面跳转
74LS373 PDF预览

74LS373

更新时间: 2024-11-05 22:53:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器输出元件
页数 文件大小 规格书
7页 252K
描述
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT

74LS373 数据手册

 浏览型号74LS373的Datasheet PDF文件第2页浏览型号74LS373的Datasheet PDF文件第3页浏览型号74LS373的Datasheet PDF文件第4页浏览型号74LS373的Datasheet PDF文件第5页浏览型号74LS373的Datasheet PDF文件第6页浏览型号74LS373的Datasheet PDF文件第7页 
SN54/74LS373  
SN54/74LS374  
OCTAL TRANSPARENT LATCH  
WITH 3-STATE OUTPUTS;  
OCTAL D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUT  
OCTAL TRANSPARENT LATCH  
WITH 3-STATE OUTPUTS;  
OCTAL D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUT  
The SN54/74LS373 consists of eight latches with 3-state outputs for bus  
organized system applications. The flip-flops appear transparent to the data  
(data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is  
LOW, the data that meets the setup times is latched. Data appears on the bus  
when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in  
the high impedance state.  
LOW POWER SCHOTTKY  
The SN54/74LS374 is a high-speed, low-power Octal D-type Flip-Flop fea-  
turing separate D-type inputs for each flip-flop and 3-state outputs for bus ori-  
entedapplications. Abuffered Clock (CP) and Output Enable (OE) is common  
to all flip-flops. The SN54/74LS374 is manufactured using advanced Low  
Power Schottky technology and is compatible with all Motorola TTL families.  
J SUFFIX  
CERAMIC  
CASE 732-03  
20  
1
Eight Latches in a Single Package  
3-State Outputs for Bus Interfacing  
Hysteresis on Latch Enable  
Edge-Triggered D-Type Inputs  
Buffered Positive Edge-Triggered Clock  
Hysteresis on Clock Input to Improve Noise Margin  
Input Clamp Diodes Limit High Speed Termination Effects  
N SUFFIX  
PLASTIC  
CASE 738-03  
20  
1
DW SUFFIX  
SOIC  
CASE 751D-03  
PIN NAMES  
LOADING (Note a)  
20  
HIGH  
LOW  
1
D D  
0
Data Inputs  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
7
LE  
Latch Enable (Active HIGH) Input  
Clock (Active HIGH going edge) Input  
Output Enable (Active LOW) Input  
Outputs (Note b)  
CP  
OE  
O O  
0
0.5 U.L.  
0.25 U.L.  
ORDERING INFORMATION  
65 (25) U.L.  
15 (7.5) U.L.  
7
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXDW SOIC  
NOTES:  
a) 1 TTL Units Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 25 U.L. for Commercial  
(74) Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military (54) and  
65 U.L. for Commercial (74) Temperature Ranges.  
CONNECTION DIAGRAM DIP (TOP VIEW)  
SN54/74LS374  
SN54/74LS373  
NOTE:  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
FAST AND LS TTL DATA  
5-521  

与74LS373相关器件

型号 品牌 获取价格 描述 数据表
74LS373DC ROCHESTER

获取价格

Bus Driver,
74LS373DCQM FAIRCHILD

获取价格

Bus Driver, 1-Func, 8-Bit, TTL, CDIP20,
74LS373FC FAIRCHILD

获取价格

Bus Driver, 1-Func, 8-Bit, TTL, CDFP20,
74LS373FCQM ROCHESTER

获取价格

Bus Driver,
74LS373PC ETC

获取价格

8-Bit D-Type Latch
74LS373PCQM FAIRCHILD

获取价格

Bus Driver, 1-Func, 8-Bit, TTL, PDIP20,
74LS373PCQR FAIRCHILD

获取价格

Bus Driver, 1-Func, 8-Bit, TTL, PDIP20,
74LS373SC FAIRCHILD

获取价格

Bus Driver, 1-Func, 8-Bit, TTL, PDSO20,
74LS374 HITACHI

获取价格

Octal D-type Edge-triggered Flip-Flips(with three-state outputs)
74LS374 FAIRCHILD

获取价格

3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops