5秒后页面跳转
74LS259 PDF预览

74LS259

更新时间: 2024-01-21 09:37:36
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
6页 62K
描述
8-Bit Addressable Latches

74LS259 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.69逻辑集成电路类型:D LATCH

74LS259 数据手册

 浏览型号74LS259的Datasheet PDF文件第2页浏览型号74LS259的Datasheet PDF文件第3页浏览型号74LS259的Datasheet PDF文件第4页浏览型号74LS259的Datasheet PDF文件第5页浏览型号74LS259的Datasheet PDF文件第6页 
August 1986  
Revised March 2000  
DM74LS259  
8-Bit Addressable Latches  
General Description  
Features  
These 8-bit addressable latches are designed for general  
purpose storage applications in digital systems. Specific  
uses include working registers, serial-holding registers,  
and active-high decoders or demultiplexers. They are mul-  
tifunctional devices capable of storing single-line data in  
eight addressable latches, and being a 1-of-8 decoder or  
demultiplexer with active-high outputs.  
8-Bit parallel-out storage register performs serial-to-par-  
allel conversion with storage  
Asynchronous parallel clear  
Active high decoder  
Enable/disable input simplifies expansion  
Direct replacement for Fairchild DM9334  
Expandable for N-bit applications  
Four distinct functional modes  
Typical propagation delay times:  
Enable-to-output 18 ns  
Four distinct modes of operation are selectable by control-  
ling the clear and enable inputs as enumerated in the func-  
tion table. In the addressable-latch mode, data at the data-  
in terminal is written into the addressed latch. The  
addressed latch will follow the data input with all unad-  
dressed latches remaining in their previous states. In the  
memory mode, all latches remain in their previous states  
and are unaffected by the data or address inputs. To elimi-  
nate the possibility of entering erroneous data in the  
latches, the enable should be held HIGH (inactive) while  
the address lines are changing. In the 1-of-8 decoding or  
demultiplexing mode, the addressed output will follow the  
level of the D input with all other outputs LOW. In the clear  
mode, all outputs are LOW and unaffected by the address  
and data inputs.  
Data-to-output  
16 ns  
Address-to-output 21 ns  
Clear-to-output  
Fan-out  
17 ns  
8 mA  
IOL (sink current)  
IOH (source current) 0.4 mA  
Typical ICC 22 mA  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS259M  
DM74LS259WM  
DM74LS259N  
M16A  
M16B  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2000 Fairchild Semiconductor Corporation  
DS006418  
www.fairchildsemi.com  

与74LS259相关器件

型号 品牌 获取价格 描述 数据表
74LS259DC ETC

获取价格

Addressable D-Type Latch
74LS259DCQM FAIRCHILD

获取价格

暂无描述
74LS259DCQR FAIRCHILD

获取价格

暂无描述
74LS259FCQM FAIRCHILD

获取价格

D Latch, 1-Func, 8-Bit, TTL, CDFP16,
74LS259PC ETC

获取价格

Addressable D-Type Latch
74LS259PCQM FAIRCHILD

获取价格

D Latch, 1-Func, 8-Bit, TTL, PDIP16,
74LS259PCQR FAIRCHILD

获取价格

暂无描述
74LS260 MOTOROLA

获取价格

DUAL 5-INPUT NOR GATE
74LS260A NXP

获取价格

LS SERIES, DUAL 5-INPUT NOR GATE, PDIP14
74LS260DC FAIRCHILD

获取价格

NOR Gate, TTL, CDIP14,