Datasheet > 74LS196

74LS196

更新时间： 2024-11-17 22:53:15

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		计数器
页数	文件大小	规格书
8页	229K
描述
4-STAGE PRESETTABLE RIPPLE COUNTERS

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中文翻译

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数据手册

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74LS196 数据手册

SN54/74LS196

SN54/74LS197

4-STAGE PRESETTABLE

RIPPLE COUNTERS

TheSN54/74LS196decadecounterispartitionedintodivide-by-twoanddi-

vide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1)

sequence or in a bi-quinary mode producing a 50% duty cycle output. The

SN54/74LS197 contains divide-by-two and divide-by-eight sections which

can be combined to form a modulo-16 binary counter. Low Power Schottky

technology is used to achieve typical count rates of 70 MHz and power dis-

sipation of only 80 mW.

4-STAGE PRESETTABLE

RIPPLE COUNTERS

LOW POWER SCHOTTKY

Both circuit types have a Master Reset (MR) input which overrides all other

inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL)

overrides clocked operations and asynchronously loads the data on the Par-

allel Data inputs (P ) into the flip-flops. This preset feature makes the circuits

J SUFFIX

CERAMIC

CASE 632-08

usable as programmable counters. The circuits can also be used as 4-bit

latches, loading data from the Parallel Data inputs when PL is LOW and stor-

ing the data when PL is HIGH.

• Low Power Consumption — Typically 80 mW

• High Counting Rates — Typically 70 MHz

• Choice of Counting Modes — BCD, Bi-Quinary, Binary

• Asynchronous Presettable

• Asynchronous Master Reset

• Easy Multistage Cascading

N SUFFIX

PLASTIC

CASE 646-06

• Input Clamp Diodes Limit High Speed Termination Effects

CONNECTION DIAGRAM DIP (TOP VIEW)

D SUFFIX

SOIC

CASE 751A-02

NOTE:

The Flatpak version

has the same pinouts

(Connection Diagram) as

the Dual In-Line Package.

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

SN74LSXXXN Plastic

SN74LSXXXD SOIC

PIN NAMES

LOADING (Note a)

LOGIC SYMBOL

HIGH

LOW

1.5 U.L.

Clock (Active LOW Going Edge)

Input to Divide-by-Two Section

Clock (Active LOW Going Edge)

Input to Divide-by-Five Section

Clock (Active LOW Going Edge)

Input to Divide-by-Eight Section

Master Reset (Active LOW) Input

Parallel Load (Active LOW) Input

Data Inputs

1.0 U.L.

CP (LS196)

2.0 U.L.

1.0 U.L.

1.75 U.L.

0.8 U.L.

CP (LS197)

1.0 U.L.

0.5 U.L.

10 U.L.

0.5 U.L.

0.25 U.L.

P –P

0.25 U.L.

Q –Q

Outputs (Notes b, c)

5 (2.5) U.L.

NOTES:

a. 1 TTL Unit Load (U.L.) = 40µA HIGH/1.6 mA LOW.

b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

b. Temperature Ranges.

c. In addition to loading shown, Q can also drive CP .

FAST AND LS TTL DATA

5-372

12 3 4 5 6 7 8

中文翻译

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与74LS196相关器件

型号	品牌	获取价格	描述	数据表
74LS196A	NXP	获取价格	IC LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, PDIP14, Counter
74LS196D	ROCHESTER	获取价格	Binary Counter,
74LS196DC	FAIRCHILD	获取价格	Decade Counter, Asynchronous, Up Direction, TTL, CDIP14,
74LS196DCQM	FAIRCHILD	获取价格	Decade Counter, Asynchronous, Up Direction, TTL, CDIP14,
74LS196DCQR	FAIRCHILD	获取价格	Decade Counter, Asynchronous, Up Direction, TTL, CDIP14,
74LS196FCQR	FAIRCHILD	获取价格	Decade Counter, Asynchronous, Up Direction, TTL, CDFP14,
74LS196N	ROCHESTER	获取价格	Binary Counter,
74LS196N	RAYTHEON	获取价格	Decade Counter, Asynchronous, Up Direction, TTL, PDIP14,
74LS196NA+1	RAYTHEON	获取价格	Decade Counter, Asynchronous, Up Direction, TTL, PDIP14,
74LS196NA+2	RAYTHEON	获取价格	Decade Counter, Asynchronous, Up Direction, TTL, PDIP14,

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